公开(公告)号：US12292752B2

公开(公告)日：2025-05-06

申请号：US17031446

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Aurelien Mozipo ,  Archanna Srinivasan ,  Guang Chen ,  Janani Chandrasekhar

IPC: G05F1/56 ,  H03K17/22 ,  H03K19/17736

Abstract: An electronic system includes first, second, third, and fourth integrated circuit dies. The third integrated circuit die has a first voltage regulator circuit. A supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a supply voltage input of the first integrated circuit die. The first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage. The fourth integrated circuit die has a second voltage regulator circuit that generates a second supply voltage in response to the first power ready signal. A supply voltage output of the second voltage regulator circuit is coupled to provide the second supply voltage to a supply voltage input of the second integrated circuit die.

公开(公告)号：US20190044514A1

公开(公告)日：2019-02-07

申请号：US15852814

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Guang Chen ,  Jun Pin Tan

IPC: H03K19/003 ,  H03K19/177 ,  H03K19/00

Abstract: An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.

公开(公告)号：US12253870B2

公开(公告)日：2025-03-18

申请号：US17352194

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

IPC: G05F1/575 ,  G05F1/577 ,  H01L25/065 ,  H03K19/00

Abstract: A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

公开(公告)号：US20220215147A1

公开(公告)日：2022-07-07

申请号：US17703181

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Teik Wah Lim ,  Rajiv Mongia ,  Archanna Srinivasan ,  Mahesh A. Iyer

IPC: G06F30/32 ,  G06F30/343

Abstract: An integrated circuit system includes a temperature sensor circuit that generates an output indicative of a temperature in an integrated circuit. The integrated circuit system also includes a temperature management controller circuit that compares the temperature indicated by the output of the temperature sensor circuit to a temperature threshold. The integrated circuit system further includes temperature reduction circuitry and/or design compilation techniques and partial or full reconfiguration that controls the temperature in the integrated circuit system. The temperature management controller circuit causes the temperature reduction circuitry to reduce the temperature in response to the temperature indicated by the output of the temperature sensor circuit exceeding the temperature threshold. The temperature sensor circuit, the temperature management controller circuit, and the temperature reduction circuitry may be implemented by soft logic circuits, hard logic circuits, or any combination thereof.

公开(公告)号：US20210313988A1

公开(公告)日：2021-10-07

申请号：US17354473

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Scott Weber ,  Aravind Dasu ,  Ravi Gutala ,  Mahesh Iyer ,  Eriko Nurvitadhi ,  Archanna Srinivasan ,  Sean Atsatt ,  James Ball

IPC: H03K19/17736 ,  H03K19/1776 ,  H03K19/17768 ,  H01L25/18

Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.

公开(公告)号：US20210311537A1

公开(公告)日：2021-10-07

申请号：US17351747

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

IPC: G06F1/28 ,  H01L25/065 ,  G05F1/66 ,  H03K19/00

Abstract: A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.

公开(公告)号：US10243561B2

公开(公告)日：2019-03-26

申请号：US15852814

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Guang Chen ,  Jun Pin Tan

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/177 ,  G11C7/00

Abstract: An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.

公开(公告)号：US12255648B2

公开(公告)日：2025-03-18

申请号：US17350577

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

IPC: H03K19/17788 ,  H03K19/17728 ,  H03K19/17792

Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

公开(公告)号：US20230100829A1

公开(公告)日：2023-03-30

申请号：US18070361

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Sheue Fen Yong ,  Archanna Srinivasan ,  Graham Baker ,  Pheak Ti Teh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: An integrated circuit package includes a first integrated circuit die, a spacer die coupled in the integrated circuit package in a location designed to house a second integrated circuit die, and a package substrate coupled to the first integrated circuit die and to the spacer die.

公开(公告)号：US20210313991A1

公开(公告)日：2021-10-07

申请号：US17350577

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

IPC: H03K19/17788 ,  H03K19/17792 ,  H03K19/17728

Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.