-
1.
公开(公告)号:US20220393685A1
公开(公告)日:2022-12-08
申请号:US17891154
申请日:2022-08-19
发明人: Grant Thomas Jennings , Jinghui Zhu
IPC分类号: H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
摘要: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
-
2.
公开(公告)号:US11496135B2
公开(公告)日:2022-11-08
申请号:US17325025
申请日:2021-05-19
发明人: Grant Thomas Jennings , Jinghui Zhu
IPC分类号: H03K19/177 , H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
摘要: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
-
公开(公告)号:US20220123976A1
公开(公告)日:2022-04-21
申请号:US17419138
申请日:2020-01-06
发明人: Vivek Mangal , Peter R. Kinget
IPC分类号: H04L27/06 , H04L27/26 , H03K19/17788 , H03K19/0185
摘要: Circuit for wake-up receivers are provide. In some embodiments, the wake-up receivers include self-mixers that receive a gate bias voltage. Some of the self-mixers are single ended and some are differential. In some embodiments, the wake-up receivers include a matching network that is connected to the input of the self-mixer. In some embodiments, the wake-up receivers include a low frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers include a high frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers are configured to receive an encoded bit stream. In some embodiments, the wake-up receivers are configured to wake-up another receiver.
-
公开(公告)号:US11791824B1
公开(公告)日:2023-10-17
申请号:US17741477
申请日:2022-05-11
申请人: Apple Inc.
发明人: Sharon D Mutchnik
IPC分类号: H03K19/17788
CPC分类号: H03K19/17788
摘要: An integrated circuit (IC) includes an Input/Output (I/O) interface, first-domain circuitry and second-domain circuitry. The I/O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I/O interface with the bit value.
-
5.
公开(公告)号:US11664806B2
公开(公告)日:2023-05-30
申请号:US17891154
申请日:2022-08-19
发明人: Grant Thomas Jennings , Jinghui Zhu
IPC分类号: H03K19/177 , H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
CPC分类号: H03K19/17788 , H03K19/1776 , H03K19/17708 , H03K19/17784
摘要: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
-
公开(公告)号:US10804903B1
公开(公告)日:2020-10-13
申请号:US16684961
申请日:2019-11-15
申请人: Jia Di , Andrew Lloyd Suchanek , Zhong Chen , Matthew Leftwich
发明人: Jia Di , Andrew Lloyd Suchanek , Zhong Chen , Matthew Leftwich
IPC分类号: H03K19/17784 , H03K19/17788 , H03K19/08
摘要: A circuit stacking multiple asynchronous circuit components, specifically Multi-Threshold NULL Convention Logic (MTNCL) circuit components, with an overall power supply equal to the multiples of the original VDD.
-
公开(公告)号:US20200244266A1
公开(公告)日:2020-07-30
申请号:US16849810
申请日:2020-04-15
申请人: SK hynix Inc.
发明人: Seung Ho LEE
IPC分类号: H03K19/003 , H03K19/17788 , H03K19/017 , H03K19/00
摘要: An input/output driving circuit may include a pad, an open-drain driving circuit, a high-voltage protection unit and a control unit. The open-drain driving circuit may be configured to output a transmission signal to the pad. The high-voltage protection unit may be configured to input a received signal from the pad. The control unit may include a gate control logic, a transmission control logic and an inverter for controlling the open-drain driving circuit. The control unit may also include a reception control logic and a well voltage generation unit for controlling the high-voltage protection unit.
-
公开(公告)号:US10673436B1
公开(公告)日:2020-06-02
申请号:US16538513
申请日:2019-08-12
IPC分类号: H03K19/007 , H03K17/0814 , H03K3/3562 , H03K19/17788
摘要: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.
-
公开(公告)号:US20240313777A1
公开(公告)日:2024-09-19
申请号:US18674934
申请日:2024-05-27
申请人: SK hynix Inc.
发明人: Seung Ho LEE
IPC分类号: H03K19/003 , H03K19/00 , H03K19/017 , H03K19/17788
CPC分类号: H03K19/00315 , H03K19/0005 , H03K19/01742 , H03K19/17788
摘要: A memory system may include a memory device and a memory controller. The memory device may be configured to store data. The memory controller may be configured to communicate with the memory device by an input/output driving circuit. The input/output driving circuit comprises a pull-down driver and a gate control logic. The pull-down driver may include a first transistor and a second transistor which are electrically coupled between a pad and a ground node. The gate control logic including a third transistor and a fourth transistor which are electrically coupled 10 between the pad and a first terminal receiving a first driving voltage, the gate control logic being configured to receive a pad voltage provided from the pad and generate a feedback voltage. The source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.
-
公开(公告)号:US11764789B2
公开(公告)日:2023-09-19
申请号:US17487569
申请日:2021-09-28
发明人: Rajesh Mangalore Anand , Prasant Kumar Vallur , Piyush Gupta , Girish Anathahalli Singrigowda , Jagadeesh Anathahalli Singrigowda
IPC分类号: H03K19/17788 , H03K19/0185 , H03K19/003
CPC分类号: H03K19/17788 , H03K19/00315 , H03K19/00384 , H03K19/018507
摘要: Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.
-
-
-
-
-
-
-
-
-