公开(公告)号：US20220393685A1

公开(公告)日：2022-12-08

申请号：US17891154

申请日：2022-08-19

申请人： GOWIN Semiconductor Corporation

发明人： Grant Thomas Jennings ,  Jinghui Zhu

IPC分类号： H03K19/17788 ,  H03K19/1776 ,  H03K19/17704 ,  H03K19/17784

摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

公开(公告)号：US11496135B2

公开(公告)日：2022-11-08

申请号：US17325025

申请日：2021-05-19

申请人： GOWIN Semiconductor Corporation

发明人： Grant Thomas Jennings ,  Jinghui Zhu

IPC分类号： H03K19/177 ,  H03K19/17788 ,  H03K19/1776 ,  H03K19/17704 ,  H03K19/17784

摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

公开(公告)号：US20220123976A1

公开(公告)日：2022-04-21

申请号：US17419138

申请日：2020-01-06

申请人： The Trustees of Columbia University in the City of New York

发明人： Vivek Mangal ,  Peter R. Kinget

IPC分类号： H04L27/06 ,  H04L27/26 ,  H03K19/17788 ,  H03K19/0185

摘要： Circuit for wake-up receivers are provide. In some embodiments, the wake-up receivers include self-mixers that receive a gate bias voltage. Some of the self-mixers are single ended and some are differential. In some embodiments, the wake-up receivers include a matching network that is connected to the input of the self-mixer. In some embodiments, the wake-up receivers include a low frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers include a high frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers are configured to receive an encoded bit stream. In some embodiments, the wake-up receivers are configured to wake-up another receiver.

公开(公告)号：US10804903B1

公开(公告)日：2020-10-13

申请号：US16684961

申请日：2019-11-15

申请人： Jia Di ,  Andrew Lloyd Suchanek ,  Zhong Chen ,  Matthew Leftwich

发明人： Jia Di ,  Andrew Lloyd Suchanek ,  Zhong Chen ,  Matthew Leftwich

IPC分类号： H03K19/17784 ,  H03K19/17788 ,  H03K19/08

摘要： A circuit stacking multiple asynchronous circuit components, specifically Multi-Threshold NULL Convention Logic (MTNCL) circuit components, with an overall power supply equal to the multiples of the original VDD.

公开(公告)号：US20200244266A1

公开(公告)日：2020-07-30

申请号：US16849810

申请日：2020-04-15

申请人： SK hynix Inc.

发明人： Seung Ho LEE

IPC分类号： H03K19/003 ,  H03K19/17788 ,  H03K19/017 ,  H03K19/00

摘要： An input/output driving circuit may include a pad, an open-drain driving circuit, a high-voltage protection unit and a control unit. The open-drain driving circuit may be configured to output a transmission signal to the pad. The high-voltage protection unit may be configured to input a received signal from the pad. The control unit may include a gate control logic, a transmission control logic and an inverter for controlling the open-drain driving circuit. The control unit may also include a reception control logic and a well voltage generation unit for controlling the high-voltage protection unit.

公开(公告)号：US10673436B1

公开(公告)日：2020-06-02

申请号：US16538513

申请日：2019-08-12

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bharat Gajanan Hegde ,  Devraj Matharampallil Rajagopal ,  Srikanth Srinivasan

IPC分类号： H03K19/007 ,  H03K17/0814 ,  H03K3/3562 ,  H03K19/17788

摘要： A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

公开(公告)号：US20220294445A1

公开(公告)日：2022-09-15

申请号：US17534750

申请日：2021-11-24

申请人： SK hynix Inc.

发明人： Hee Jun KIM

IPC分类号： H03K19/017 ,  H03K19/17788 ,  H03K19/17784

摘要： A computer system may include a host device including a memory controller and a first interface circuit configured to provide the memory controller with an interface to other devices; and a data storage unit in communication with the host device through a channel and configured to communicate with the host device through a second interface circuit including a termination circuit. The first interface circuit is configured to select between different termination schemes. The first interface circuit is configured to add an addition signal to a transmission signal based on a termination scheme of the termination circuit and transmit the transmission signal with the addition signal to the termination circuit.

公开(公告)号：US11387830B2

公开(公告)日：2022-07-12

申请号：US16989468

申请日：2020-08-10

申请人： SK hynix Inc.

发明人： Seung Ho Lee

IPC分类号： G05F1/10 ,  H03K19/003 ,  H03K19/17788 ,  H03K19/017 ,  H03K19/00

摘要： A semiconductor memory device has an output driving circuit. The output driving circuit includes a pull-down driver and a gate control logic. The pull-down driver includes first and second transistors. The first and second transistors are coupled between a pad and a ground node. The gate control logic includes third and fourth transistors. The third and fourth transistors are coupled between a pad and a first supply voltage node. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage. The first transistor is controlled by the feedback voltage. The second and third transistors are controlled by the first supply voltage. The fourth transistor is controlled by the voltage of the pad.

公开(公告)号：US11356098B2

公开(公告)日：2022-06-07

申请号：US17353917

申请日：2021-06-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byongmo Moon ,  Jiyoung Kim ,  Seongook Jung ,  Jongsoo Lee

IPC分类号： G11C7/10 ,  H03K19/173 ,  H03K19/0175 ,  G11C7/22 ,  H03K19/17788 ,  G11C7/14 ,  H03K19/017

摘要： A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

公开(公告)号：US20210376834A1

公开(公告)日：2021-12-02

申请号：US17325025

申请日：2021-05-19

申请人： GOWIN Semiconductor Corporation

发明人： Grant Thomas Jennings ,  Jinghui Zhu

IPC分类号： H03K19/17788 ,  H03K19/17784 ,  H03K19/17704 ,  H03K19/1776

摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.