公开(公告)号：US20240192954A1

公开(公告)日：2024-06-13

申请号：US18444254

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Mark J. CHARNEY ,  Elmoustapha OULD-AHMED-VALL ,  Dan BAUM ,  Zeev SPERBER ,  Jesus CORBAL ,  Bret L. TOLL ,  Raanan SADE ,  Igor YANOVER ,  Yuri GEBIL ,  Rinat RAPPOPORT ,  Stanislav SHWARTSMAN ,  Menachem ADELMAN ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US20230236833A1

公开(公告)日：2023-07-27

申请号：US18100194

申请日：2023-01-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Milind B. GIRKAR ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Rinat RAPPOPORT ,  Jesus Corbal ,  Stanislav SHWARTSMAN ,  Dan BAUM ,  Igor YANOVER ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Elmoustapha OULD-AHMED-VALL ,  Yuri GEBIL

IPC: G06F9/30 ,  G06F7/485 ,  G06F17/16 ,  G06F7/76 ,  G06F7/487 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F17/16 ,  G06F9/30112 ,  G06F7/762 ,  G06F9/3016 ,  G06F9/30196 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30185 ,  G06F7/4876 ,  G06F9/30145 ,  G06F9/30134 ,  G06F9/30149 ,  G06F9/3836 ,  G06F9/30032 ,  G06F9/3001 ,  G06F9/3818 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：US20230102279A1

公开(公告)日：2023-03-30

申请号：US17485363

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Robert VALENTINE ,  Dan BAUM ,  Amit GRADSTEIN ,  Simon RUBANOVICH ,  Regev SHEMY ,  Zeev SPERBER ,  Alexander HEINECKE ,  Christopher HUGHES ,  Evangelos GEORGANAS ,  Mark CHARNEY ,  Arik NARKIS ,  Rinat RAPPOPORT ,  Barukh ZIV ,  Yaroslav POLLAK ,  Nilesh JAIN ,  Yash AKHAURI ,  Brinda GANESH ,  Rajesh POORNACHANDRAN ,  Guy BOUDOUKH

IPC: G06F9/30 ,  G06F17/16

Abstract: Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.

公开(公告)号：US20200233666A1

公开(公告)日：2020-07-23

申请号：US16487755

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Milind B. GIRKAR ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Rinat RAPPOPORT ,  Jesus CORBAL ,  Stanislav SHWARTSMAN ,  Igor YANOVER ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Dan BAUM ,  Yuri GEBIL

IPC: G06F9/30 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information

公开(公告)号：US20190042448A1

公开(公告)日：2019-02-07

申请号：US15853640

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Raanan SADE ,  Jason BRANDT ,  Mark J. CHARNEY ,  Joseph NUZMAN ,  Leena PUTHIYEDATH ,  Rinat RAPPOPORT ,  Vivekananthan SANJEEPAN ,  Robert VALENTINE

IPC: G06F12/0877 ,  G06F12/0846 ,  G06F12/0813 ,  G06F12/0895 ,  G06F9/30

Abstract: Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.