公开(公告)号：US20190280813A1

公开(公告)日：2019-09-12

申请号：US16420504

申请日：2019-05-23

Applicant: Intel Corporation

Inventor： Vivek Joy Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Dinesh Somasekhar ,  Melin Dadual

IPC: H04L1/00

Abstract: Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.

公开(公告)号：US20180285304A1

公开(公告)日：2018-10-04

申请号：US15475571

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Kon-Woo Kwon ,  Dinesh Somasekhar

IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.