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公开(公告)号：US10862622B2
公开(公告)日：2020-12-08
申请号：US16420504
申请日：2019-05-23
Applicant: Intel Corporation
IPC: H04L1/00
Abstract: Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.
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公开(公告)号：US20200285599A1
公开(公告)日：2020-09-10
申请号：US16663134
申请日：2019-10-24
Applicant: Intel Corporation
Inventor： Melin Dadual , Vivek Joy Kozhikkottu , Shankar Ganesh Ramasubramanian
IPC: G06F13/40 , G06F13/374 , G06F13/42 , G06F1/26 , G06F1/3234
Abstract: A device includes a driver circuit to send data bits onto a data bus that is partitioned into a DC component and an AC component. The driver circuit is to, for some data bits, retrieve a value of a DC power ratio of the data bus. The driver circuit is further to determine, using the value of the DC power ratio, a first value for a first portion of total power to be dissipated over the DC component to transmit the data bits, and determine, using one minus the value of the DC power ratio, a second value for a second portion of total power to be dissipated over the AC component to transmit the data bits. The driver circuit is to determine whether to send the data bits onto the data bus using data bus inversion dependent on a combination of the first value and the second value.
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公开(公告)号：US11216386B2
公开(公告)日：2022-01-04
申请号：US16584612
申请日：2019-09-26
Applicant: Intel Corporation
Inventor： Vivek Kozhikkottu , Suresh Chittor , Esha Choukse , Shankar Ganesh Ramasubramanian
Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.
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公开(公告)号：US10853300B2
公开(公告)日：2020-12-01
申请号：US15475571
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Vivek Kozhikkottu , Shankar Ganesh Ramasubramanian , Kon-Woo Kwon , Dinesh Somasekhar
Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.
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公开(公告)号：US11281616B2
公开(公告)日：2022-03-22
申请号：US16663134
申请日：2019-10-24
Applicant: Intel Corporation
Inventor： Melin Dadual , Vivek Joy Kozhikkottu , Shankar Ganesh Ramasubramanian
IPC: G06F3/00 , G06F13/40 , G06F13/374 , G06F1/3234 , G06F1/26 , G06F13/42
Abstract: A device includes a driver circuit to send data bits onto a data bus that is partitioned into a DC component and an AC component. The driver circuit is to, for some data bits, retrieve a value of a DC power ratio of the data bus. The driver circuit is further to determine, using the value of the DC power ratio, a first value for a first portion of total power to be dissipated over the DC component to transmit the data bits, and determine, using one minus the value of the DC power ratio, a second value for a second portion of total power to be dissipated over the AC component to transmit the data bits. The driver circuit is to determine whether to send the data bits onto the data bus using data bus inversion dependent on a combination of the first value and the second value.
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Patent Agency Ranking
公开(公告)号：US10936507B2
公开(公告)日：2021-03-02
申请号：US16367592
申请日：2019-03-28
Applicant: Intel Corporation
Inventor： Vivek Kozhikkottu , Esha Choukse , Shankar Ganesh Ramasubramanian , Melin Dadual , Suresh Chittor
IPC: G06F12/10 , G06F12/1009 , G06F16/907 , G06F9/54 , G06F12/0873 , G06F9/4401
Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.
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公开(公告)号：US10860419B2
公开(公告)日：2020-12-08
申请号：US16236151
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Dinesh Somasekhar , Wei Wu , Shankar Ganesh Ramasubramanian , Vivek Kozhikkottu , Melin Dadual
Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.
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公开(公告)号：US20180188976A1
公开(公告)日：2018-07-05
申请号：US15395615
申请日：2016-12-30
Applicant: Intel Corporation
Inventor： Gunjae Koo , Vivek Kozhikkottu , Shankar Ganesh Ramasubramanian , Christopher B. Wilkerson
CPC classification number: G06F12/06 , G06F12/0215 , G06F13/16 , G06F13/1642 , G06F2212/1016 , G06F2212/1041
Abstract: Devices, systems, and methods for increasing the size of a read pending queue (RPQ) in a memory controller are described. An example of increasing the RPQ size can include receiving, at a memory controller, a read request for data in a memory having a physical address identification (ID) including row and column ID, performing a lookup of the RPQ for an entry having a pending read transaction with a physical address ID having the same row ID as the incoming read request, and, if the RPQ lookup returns a hit, appending the incoming read request's column ID to the physical address ID of the pending read transaction to form an appended read transaction. The appending read transaction can then be queued and processed sequentially, while occupying a single RPQ entry.
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公开(公告)号：US20200310979A1
公开(公告)日：2020-10-01
申请号：US16367592
申请日：2019-03-28
Applicant: Intel Corporation
Inventor： Vivek Kozhikkottu , Esha Choukse , Shankar Ganesh Ramasubramanian , Melin Dadual , Suresh Chittor
IPC: G06F12/1009 , G06F12/0873 , G06F16/907 , G06F9/54
Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.
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公开(公告)号：US20200210284A1
公开(公告)日：2020-07-02
申请号：US16236151
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Dinesh Somasekhar , Wei Wu , Shankar Ganesh Ramasubramanian , Vivek Kozhikkottu , Melin Dadual
Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.
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