Method for designing cell layout of semiconductor integrated circuit
    11.
    发明授权
    Method for designing cell layout of semiconductor integrated circuit 有权
    半导体集成电路单元布局设计方法

    公开(公告)号:US08230381B2

    公开(公告)日:2012-07-24

    申请号:US12773260

    申请日:2010-05-04

    IPC分类号: G06F17/50 G06F9/455

    CPC分类号: G06F17/5068

    摘要: With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the conventional method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. To avoid these problems, cells of a specific type specified from outside, or cells satisfying specific conditions, are extracted and arranged first or limited to a layout position by specifying a layout position, then arranging the remaining cells using a general layout algorithm.

    摘要翻译: 利用用于设计单元布局的常规方法,需要预先给予要布置的所有单元的相对位置信息。 此外,常规方法是麻烦的,因为在确认临时布局的结果之后需要校正单元的相对位置信息。 因此,获取布局结果需要时间。 为了避免这些问题,通过指定布局位置,提取并排列从外部指定的特定类型的单元格或者满足特定条件的单元格,或者通过布局位置来限制布局位置,然后使用通用布局算法布置剩余单元格。

    METHOD FOR DESIGNING CELL LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT
    12.
    发明申请
    METHOD FOR DESIGNING CELL LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    用于设计半导体集成电路的单元布局的方法

    公开(公告)号:US20100218154A1

    公开(公告)日:2010-08-26

    申请号:US12773260

    申请日:2010-05-04

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the conventional method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. To avoid these problems, cells of a specific type specified from outside, or cells satisfying specific conditions, are extracted and arranged first or limited to a layout position by specifying a layout position, then arranging the remaining cells using a general layout algorithm.

    摘要翻译: 利用用于设计单元布局的常规方法,需要预先给予要布置的所有单元的相对位置信息。 此外,常规方法是麻烦的,因为在确认临时布局的结果之后需要校正单元的相对位置信息。 因此,获取布局结果需要时间。 为了避免这些问题,通过指定布局位置,提取并排列从外部指定的特定类型的单元格或者满足特定条件的单元格,或者通过布局位置来限制布局位置,然后使用通用布局算法布置剩余单元格。

    Wiring pattern decision method considering electrical length and multi-layer wiring board

    公开(公告)号:US06640332B2

    公开(公告)日:2003-10-28

    申请号:US09864865

    申请日:2001-05-23

    IPC分类号: G06F1750

    摘要: A method for determining a wiring pattern of a signal line for connection of a circuit on a multi-layer printed wiring board includes the steps of providing a constraint of an electrical length which the signal line must satisfy, determining an electrical length change at a discontinuous delay part of the signal line along which a signal propagates, determining a wiring route of the signal line, calculating an electrical length of the signal line with use of a wiring length of the signal line and the determined electrical length change, judging whether or not the calculated electrical length satisfies the electrical length constraint given to the signal line, and determining the wiring route as a wiring pattern when the electrical length constraint is satisfied as the decision result, thereby carrying out a wiring layout to make an electrical length constraint satisfied.

    Method of forming a resist pattern
    14.
    发明授权
    Method of forming a resist pattern 失效
    形成抗蚀剂图案的方法

    公开(公告)号:US5994036A

    公开(公告)日:1999-11-30

    申请号:US805153

    申请日:1997-02-24

    申请人: Katsuyuki Itoh

    发明人: Katsuyuki Itoh

    CPC分类号: G03F7/168

    摘要: A method of forming a resist pattern comprises the following steps. A resist is applied on a wafer for subsequent baking the same. Subsequently, the resist-applied wafer is then stored in an atmosphere maintained at a humidity of not less than 80% until the resist-applied wafer is placed in an exposure system for exposure thereof by use of a photo-mask. A development of the exposed resist on the wafer is carried out to form a resist pattern. It is possible to further store the wafer in a clean room before the exposure. The above resist is preferably a chemical sensitizing resist.

    摘要翻译: 形成抗蚀剂图案的方法包括以下步骤。 将抗蚀剂施加在晶片上以进行后续烘焙。 随后,将抗蚀剂涂覆的晶片保存在不低于80%湿度的气氛中,直到将抗蚀剂涂覆的晶片放置在曝光系统中,以便通过使用光掩模进行曝光。 进行在晶片上曝光的抗蚀剂的显影以形成抗蚀剂图案。 在曝光之前可以将晶片进一步存储在洁净室中。 上述抗蚀剂优选为化学增感抗蚀剂。

    Electron beam shaping mask for an electron beam system with pattern
writing capability
    15.
    发明授权
    Electron beam shaping mask for an electron beam system with pattern writing capability 失效
    具有图案写入能力的电子束系统的电子束整形掩模

    公开(公告)号:US5593761A

    公开(公告)日:1997-01-14

    申请号:US458849

    申请日:1995-06-02

    IPC分类号: H01L21/027 H01J37/09 B32B9/00

    摘要: An electron beam shaping mask for an electron beam with pattern writing capability, includes a substrate with various opening patterns and metallic films, which are respectively formed on top- and bottom-surfaces of the substrate. The metallic films serve as foundation metallic layers. According to the structure, a total thickness of the metallic layer is divided into the two thin metallic films. Since the substrate is protected from both sides by the metallic films, its thickness can be made to be thin. Therefore, a highly accurate patterning can be easily performed, and thermal stresses can be decreased and exfoliations of the metallic films can be avoided.

    摘要翻译: 具有图案写入能力的电子束的电子束整形掩模包括分别形成在衬底的顶表面和底表面上的具有各种开口图案的衬底和金属膜。 金属膜用作基础金属层。 根据该结构,将金属层的总厚度分为两个薄金属膜。 由于通过金属膜保护基板两面,所以可以使其厚度变薄。 因此,可以容易地进行高精度的图案化,并且可以降低热应力,并且可以避免金属膜的剥离。