公开(公告)号：US4527115A

公开(公告)日：1985-07-02

申请号：US452169

申请日：1982-12-22

申请人： Deepak Mehrotra ,  Rajni Kant ,  Kishor M. Patel

发明人： Deepak Mehrotra ,  Rajni Kant ,  Kishor M. Patel

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H03K19/177 ,  G01R15/12

CPC分类号： G01R31/318516

摘要： A configurable logic gate array having an array of logic gates adapted for selective electrical interconnection to provide a predetermined logic function on a plurality of input logic signals fed to the configured gate array and produce such predetermined logic function as an output signal at an array output terminal. An output buffer circuit is coupled between the output of an interconnected gate and the array output terminal. A parametric testing circuit is responsive to a control signal for electrically coupling, during a normal operating mode, the output of the interconnected gate to the array output terminal, or, during a parameter testing mode, a logic signal source for producing "high" and "low" logic output voltages representative of the logic output voltage produced by the logic gates in response to the logic input signals.With such arrangement, there is a reduction in the test program development time since bringing the output to the desired state (high or low) be sequencing through function testing to achieve the desired state on the desired pin (an error prone, time consuming process requiring full understanding of the logic implemented and rationale applied by customer in generating test vectors) is eliminated. Further, with such an arrangement, parametric testing of the output signals by the gates in the array is performed by merely driving each output buffer circuit to "high" or "low" logic states thereby reducing parametric testing time of the gate array after the logic gates have been selectively electrically interconnected to provide the desired predetermined logic function.

摘要翻译： 一种可配置的逻辑门阵列，其具有适于选择性电互连的逻辑门阵列，以向馈送到所配置的门阵列的多个输入逻辑信号提供预定的逻辑功能，并产生诸如阵列输出端的输出信号的预定逻辑功能 。 输出缓冲电路耦合在互连栅极的输出端与阵列输出端子之间。 参数测试电路响应于控制信号，用于在正常操作模式期间将互连栅极的输出电耦合到阵列输出端子，或者在参数测试模式期间，用于产生“高”和 代表由逻辑门响应逻辑输入信号产生的逻辑输出电压的“低”逻辑输出电压。 通过这种布置，测试程序开发时间有所减少，因为将输出输出到期望状态（高或低）是通过功能测试进行排序，以在期望的引脚上实现所需的状态（需要错误的，耗时的过程 全面了解客户在生成测试向量中应用的逻辑实现和理论基础）。 此外，通过这样的布置，通过仅将驱动每个输出缓冲器电路为“高”或“低”逻辑状态来执行阵列中的栅极的输出信号的参数测试，从而减少逻辑后的门阵列的参数测试时间 门已经选择性地电互连以提供期望的预定逻辑功能。