公开(公告)号：US4527115A

公开(公告)日：1985-07-02

申请号：US452169

申请日：1982-12-22

申请人： Deepak Mehrotra ,  Rajni Kant ,  Kishor M. Patel

发明人： Deepak Mehrotra ,  Rajni Kant ,  Kishor M. Patel

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H03K19/177 ,  G01R15/12

CPC分类号： G01R31/318516

摘要： A configurable logic gate array having an array of logic gates adapted for selective electrical interconnection to provide a predetermined logic function on a plurality of input logic signals fed to the configured gate array and produce such predetermined logic function as an output signal at an array output terminal. An output buffer circuit is coupled between the output of an interconnected gate and the array output terminal. A parametric testing circuit is responsive to a control signal for electrically coupling, during a normal operating mode, the output of the interconnected gate to the array output terminal, or, during a parameter testing mode, a logic signal source for producing "high" and "low" logic output voltages representative of the logic output voltage produced by the logic gates in response to the logic input signals.With such arrangement, there is a reduction in the test program development time since bringing the output to the desired state (high or low) be sequencing through function testing to achieve the desired state on the desired pin (an error prone, time consuming process requiring full understanding of the logic implemented and rationale applied by customer in generating test vectors) is eliminated. Further, with such an arrangement, parametric testing of the output signals by the gates in the array is performed by merely driving each output buffer circuit to "high" or "low" logic states thereby reducing parametric testing time of the gate array after the logic gates have been selectively electrically interconnected to provide the desired predetermined logic function.

摘要翻译： 一种可配置的逻辑门阵列，其具有适于选择性电互连的逻辑门阵列，以向馈送到所配置的门阵列的多个输入逻辑信号提供预定的逻辑功能，并产生诸如阵列输出端的输出信号的预定逻辑功能 。 输出缓冲电路耦合在互连栅极的输出端与阵列输出端子之间。 参数测试电路响应于控制信号，用于在正常操作模式期间将互连栅极的输出电耦合到阵列输出端子，或者在参数测试模式期间，用于产生“高”和 代表由逻辑门响应逻辑输入信号产生的逻辑输出电压的“低”逻辑输出电压。 通过这种布置，测试程序开发时间有所减少，因为将输出输出到期望状态（高或低）是通过功能测试进行排序，以在期望的引脚上实现所需的状态（需要错误的，耗时的过程 全面了解客户在生成测试向量中应用的逻辑实现和理论基础）。 此外，通过这样的布置，通过仅将驱动每个输出缓冲器电路为“高”或“低”逻辑状态来执行阵列中的栅极的输出信号的参数测试，从而减少逻辑后的门阵列的参数测试时间 门已经选择性地电互连以提供期望的预定逻辑功能。

公开(公告)号：US4512076A

公开(公告)日：1985-04-23

申请号：US450900

申请日：1982-12-20

申请人： Deepak Mehrotra ,  Gerard J. Shaw ,  Jok Y. Go ,  Rajni Kant

发明人： Deepak Mehrotra ,  Gerard J. Shaw ,  Jok Y. Go ,  Rajni Kant

IPC分类号： H01L27/082 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/47 ,  H01L29/73 ,  H01L29/872 ,  H01L21/86

CPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/28525

摘要： A semiconductor device fabrication process is provided wherein a first window is formed in a first silicon dioxide layer which is disposed over the surface of a silicon layer to expose a first portion of the silicon layer. A doped region is formed in the first portion of a silicon layer exposed by the first window. A second layer of silicon dioxide is deposited over the surface of the first, previously formed, silicon dioxide layer and over the first portion of the silicon layer exposed by the first window. A second window is formed through the first and second silicon dioxide layers to expose a second, different portion of the surface of the silicon layer. A layer of silicon nitride is disposed over the second layer of silicon dioxide and through the second formed window onto the portion of the silicon layer exposed by such second formed window. The surface of the structure is then masked with windows being formed in such mask over the first and second previously exposed portions of the silicon layer. An etchant is brought into contact with portions of the silicon nitride layer exposed by the windows formed in the mask to selectively remove the portions of the silicon nitride layer exposed by such windows and to thereby expose the portion of the second silicon dioxide layer disposed over the first exposed portion of the silicon layer and the second exposed portion of the silicon layer. A Schottky contact metal is deposited over the surface of the structure and onto the second exposed portion of the silicon layer to form a Schottky contact region. The portion of the second silicon dioxide layer disposed over the first exposed portion of the silicon layer is then selectively removed with a chemical etchant to expose a portion of the previously formed doped region.

摘要翻译： 提供了半导体器件制造方法，其中第一窗口形成在第一二氧化硅层中，第一二氧化硅层设置在硅层的表面上以暴露硅层的第一部分。 在由第一窗露出的硅层的第一部分中形成掺杂区域。 第二层二氧化硅沉积在第一先前形成的二氧化硅层的表面上，并且在由第一窗露出的硅层的第一部分之上。 通过第一和第二二氧化硅层形成第二窗口以暴露硅层表面的第二不同部分。 氮化硅层设置在第二二氧化硅层上并通过第二形成的窗口放置在由这种第二成形窗露出的硅层的部分上。 然后在硅层的第一和第二先前暴露部分上的这种掩模中形成窗口来掩蔽该结构的表面。 使蚀刻剂与形成在掩模中的窗口暴露的氮化硅层的部分接触，以选择性地去除由这种窗口暴露的氮化硅层的部分，从而暴露位于该掩模上的第二二氧化硅层的部分 硅层的第一暴露部分和硅层的第二暴露部分。 将肖特基接触金属沉积在结构的表面上并沉积到硅层的第二暴露部分上以形成肖特基接触区域。 然后用化学蚀刻剂选择性地去除设置在硅层的第一暴露部分上的第二二氧化硅层的部分，以暴露先前形成的掺杂区域的一部分。

公开(公告)号：US4332070A

公开(公告)日：1982-06-01

申请号：US216401

申请日：1980-12-15

申请人： Rajni Kant

发明人： Rajni Kant

IPC分类号： H01L27/08 ,  H01L29/8605 ,  H01L21/283 ,  H01L21/38

CPC分类号： H01L29/8605 ,  H01L27/0802 ,  Y10S438/934

摘要： A diffused resistor included in a Schottky device formed in a planar semiconductor material comprises a resistor diffusion formed in the surface of the material and a contact diffusion formed in the surface of the material, the configuration of the contact diffusion being essentially coincident with the shape of the resistor at the location at which ohmic contact to the resistor diffusion is made.

摘要翻译： 包括在形成在平面半导体材料中的肖特基器件中的扩散电阻器包括形成在材料表面中的电阻器扩散和形成在材料表面中的接触扩散，接触扩散的构型基本上与 在与电阻器扩散的欧姆接触的位置处的电阻器。

公开(公告)号：US4691161A

公开(公告)日：1987-09-01

申请号：US744349

申请日：1985-06-13

申请人： Rajni Kant ,  Kun-Nau Chen

发明人： Rajni Kant ,  Kun-Nau Chen

IPC分类号： H01L21/66 ,  G01R31/3185 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  G01R31/26

CPC分类号： G01R31/318516

摘要： An integrated circuit having an array of logic gates adapted to provide predetermined logic functions on a plurality of input logic signals fed to the gate array and produce such predetermined logic functions as output signals at a plurality of array output terminals. A plurality of output buffer circuits are coupled between the outputs of an interconnected gate and the array output terminals. A circuit is provided for electrically decoupling each one of the plurality of logic output buffer circuits from the plurality of array output terminals in response to a common control signal. In a preferred embodiment, the control signal is fed to a single one of the plurality of array output terminals. With such arrangement, in response to the control signal, all logic outputs of the gate array are electrically isolated from other components wired to the gate array thereby allowing diagnostic testing of these other components in spite of the fact that they are wired to the gate array. It also allows parametric testing of three-state condition of the buffers required to be three-state buffers by the customer for normal device operation.

摘要翻译： 一种具有逻辑门阵列的集成电路，其适于在馈送到门阵列的多个输入逻辑信号上提供预定的逻辑功能，并产生诸如多个阵列输出端之间的输出信号的预定逻辑功能。 多个输出缓冲电路耦合在互连栅极和阵列输出端子的输出之间。 提供电路，用于响应于公共控制信号将多个逻辑输出缓冲器电路中的每一个与多个阵列输出端子电去耦合。 在优选实施例中，控制信号被馈送到多个阵列输出端中的单个阵列输出端。 通过这样的布置，响应于控制信号，门阵列的所有逻辑输出与连接到门阵列的其它组件电隔离，从而允许这些其它组件的诊断测试，尽管它们被连接到门阵列 。 它还允许客户对正常设备操作需要三态缓冲区的缓冲区的三态条件的参数测试。

公开(公告)号：US4191964A

公开(公告)日：1980-03-04

申请号：US914637

申请日：1978-06-12

申请人： Rajni Kant

发明人： Rajni Kant

IPC分类号： H01L27/08 ,  H01L27/02

CPC分类号： H01L27/0802 ,  Y10S148/136

摘要： A diffused resistor included in a Schottky device formed in a planar semiconductor material comprises a resistor diffusion formed in the surface of the material and a contact diffusion formed in the surface of the material, the configuration of the contact diffusion being essentially coincident with the shape of the resistor at the location at which ohmic contact to the resistor diffusion is made.

摘要翻译： 包括在形成在平面半导体材料中的肖特基器件中的扩散电阻器包括形成在材料表面中的电阻器扩散和形成在材料表面中的接触扩散，接触扩散的构型基本上与 在与电阻器扩散的欧姆接触的位置处的电阻器。