公开(公告)号：US20060179237A1

公开(公告)日：2006-08-10

申请号：US11054173

申请日：2005-02-09

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  Jeffrey Stuecheli

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  Jeffrey Stuecheli

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0851

摘要： A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.

摘要翻译： 公开了一种用于在多处理器系统中执行数据预取的方法和装置。 多处理器系统包括多个处理器，每个具有高速缓冲存储器。 缓存存储器被细分成多个片段。 一组预取请求最初由多处理器系统中的请求处理器发出。 每个预取请求用于请求处理器的高速缓冲存储器的相应片段之一。 响应于在请求处理器的高速缓冲存储器中错过的预取请求，预取请求被合并成一个组合预取请求。 然后将组合的预取请求发送到多处理器系统内的所有不请求处理器的高速缓冲存储器。 响应于来自所有非请求处理器的高速缓冲存储器的组合清洁响应，然后从系统存储器获得用于组合预取请求的数据。

公开(公告)号：US20070266126A1

公开(公告)日：2007-11-15

申请号：US11279643

申请日：2006-04-13

申请人： Leo Clark ,  James Fields ,  Benjiman Goodman ,  William Starke ,  Jeffrey Stuecheli

发明人： Leo Clark ,  James Fields ,  Benjiman Goodman ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F15/173

CPC分类号： G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.

摘要翻译： 数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送 处理单位。 该通信包括具有请求的操作和表示对请求的系统响应的组合响应。 至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列 在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。 票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

公开(公告)号：US20070073998A1

公开(公告)日：2007-03-29

申请号：US11236458

申请日：2005-09-27

申请人： Vicente Chung ,  Benjiman Goodman ,  Praveen Reddy ,  William Starke

发明人： Vicente Chung ,  Benjiman Goodman ,  Praveen Reddy ,  William Starke

IPC分类号： G06F15/00

CPC分类号： G06F15/17337

摘要： A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each of the plurality of first processing units is coupled to a respective one of the plurality of second processing units in the second processing node by a respective one of a plurality of point-to-point links.

摘要翻译： 数据处理系统包括第一处理节点和第二处理节点。 第一处理节点包括彼此耦合以进行通信的多个第一处理单元，并且第二处理节点包括彼此耦合以进行通信的多个第二处理单元。 多个第一处理单元中的每一个通过多个点对点链接中的相应一个耦合到第二处理节点中的多个第二处理单元中的相应一个。

公开(公告)号：US20070061630A1

公开(公告)日：2007-03-15

申请号：US11225639

申请日：2005-09-13

申请人： James Fields ,  Benjiman Goodman ,  Praveen Reddy

发明人： James Fields ,  Benjiman Goodman ,  Praveen Reddy

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/076 ,  G06F11/0793

摘要： A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

摘要翻译： 一种用于从数据处理系统中的挂起状态恢复的数据处理系统，方法和计算机可用介质。 数据处理系统包括耦合处理单元的集合。 处理单元包括诸如两个或更多个处理核心的处理单元组件的集合，以及高速缓存阵列，处理器核心主控器，高速缓存侦听器和本地挂起管理器。 本地挂起管理器确定处理单元组件的集合中的至少一个组件是否已进入挂起状态。 如果本地挂起管理器确定至少有一个组件已进入挂起状态，则节流管理器会阻止处理单元的性能，以试图将至少一个组件从挂起状态中断。

公开(公告)号：US20060187818A1

公开(公告)日：2006-08-24

申请号：US11054288

申请日：2005-02-09

申请人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

发明人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

IPC分类号： H04J1/16

CPC分类号： G06F11/0793 ,  G06F11/0724

摘要： A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

摘要翻译： 本发明提供了一种方法，装置和计算机指令，以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功，则将第二个测试命令发送到所有处理器或其他节点，如果节点被删除。 如果第二个命令成功，则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时，控制逻辑将恢复到当前模式寄存器的值，并发送第三个测试命令来检查错误。 如果遇到错误，致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误，则使用先前配置的拓扑恢复系统操作。

公开(公告)号：US20060187939A1

公开(公告)日：2006-08-24

申请号：US11054820

申请日：2005-02-10

申请人： Benjiman Goodman ,  Praveen Reddy

发明人： Benjiman Goodman ,  Praveen Reddy

IPC分类号： H04L12/56

CPC分类号： H04L12/1881 ,  G06F12/0831 ,  H04L49/10

摘要： A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. A first processing unit in the first processing node includes interconnect logic that processes a plurality of concurrently pending broadcast operations of differing broadcast scope. At least a first of the plurality of concurrently pending broadcast operations has a first scope limited to the first processing node, and at least a second of the plurality of concurrently pending broadcast operations has a second scope including the first processing node and the second processing node.

公开(公告)号：US20060179356A1

公开(公告)日：2006-08-10

申请号：US11054275

申请日：2005-02-09

申请人： Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

发明人： Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

IPC分类号： G06F11/00

CPC分类号： G06F11/2242

摘要： A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.

摘要翻译： 一种用于系统地测试连接大量处理器的多层总线系统中所有连接的功能的方法，装置和程序。 指示每个总线控制器向所有其他处理器发送窥探请求的测试版本，并等待回复。 如果连接不良，与该连接关联的端口将超时。 检测超时将导致初始化过程停止，直到问题被隔离和解决为止。

公开(公告)号：US20070239939A1

公开(公告)日：2007-10-11

申请号：US11278825

申请日：2006-04-06

申请人： Benjiman Goodman ,  Jeffrey Stuecheli

发明人： Benjiman Goodman ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6024

摘要： An apparatus for performing stream prefetch within a multiprocessor system is disclosed. The multiprocessor system includes a first and second processors, and each of the processors includes a primary cache and a secondary cache. A stream register having multiple entries is initially provided within the first processor, and at least one of the entries in the stream register includes a prefetch history field. The bit in the prefetch history field associated with a sequential address stream is set in response to the sequential address stream being found in the secondary cache of the second processor after a system memory operation has been performed by the first processor. The bit in the prefetch history field associated with the same sequential address stream is reset in response to the sequential address stream not being found in the secondary cache of the second processor after a cache memory operation has been performed by the first processor. The bit in the prefetch history field serves as a basis for a subsequent prefetch on the same sequential address stream to decide whether the data should come from a cache memory operation or a system memory operation.

摘要翻译： 公开了一种用于在多处理器系统内执行流预取的装置。 多处理器系统包括第一和第二处理器，并且每个处理器包括主缓存和次级高速缓存。 最初在第一处理器内提供具有多个条目的流寄存器，并且流寄存器中的条目中的至少一个包括预取历史字段。 响应于在由第一处理器执行系统存储器操作之后在第二处理器的辅助高速缓存中找到顺序地址流，设置与顺序地址流相关联的预取历史字段中的位。 响应于在由第一处理器执行高速缓存存储器操作之后在第二处理器的二次高速缓存中未找到顺序地址流，复位与相同顺序地址流相关联的预取历史字段中的位。 预取历史字段中的位用作相同序列地址流上的后续预取的基础，以决定数据是来自高速缓冲存储器操作还是系统存储器操作。

公开(公告)号：US20060176886A1

公开(公告)日：2006-08-10

申请号：US11054934

申请日：2005-02-10

申请人： Benjiman Goodman ,  Praveen Reddy

发明人： Benjiman Goodman ,  Praveen Reddy

IPC分类号： H04L12/56

CPC分类号： G06F12/0813 ,  G06F12/0811 ,  G06F12/0831

摘要： A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. The first processing units in the first processing node have a first mode in which the first processing units broadcast operations with a first scope limited to the first processing node and a second mode in which the first processing units of the first processing node broadcast operations with a second scope including the first processing node and the second processing node.

公开(公告)号：US20060176885A1

公开(公告)日：2006-08-10

申请号：US11054910

申请日：2005-02-10

申请人： Benjiman Goodman ,  Praveen Reddy ,  Jeffrey Stuecheli

发明人： Benjiman Goodman ,  Praveen Reddy ,  Jeffrey Stuecheli

IPC分类号： H04L12/28

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0851

摘要： A data processing system includes an interconnect fabric, a protected resource having a plurality of banks each associated with a respective one of a plurality of address sets, a snooper that controls access to the resource, one or more masters that initiate requests, and interconnect logic coupled to the one or more masters and to the interconnect fabric. The interconnect logic regulates a rate of delivery to the snooper via the interconnect fabric of requests that target any one the plurality of banks of the protected resource.

摘要翻译： 数据处理系统包括互连结构，受保护资源具有多个存储体，每个存储体各自与多个地址集合中的相应一个地址集相关联，控制对资源的访问的监听器，发起请求的一个或多个主站和互连逻辑 耦合到一个或多个主器件和互连结构。 互连逻辑通过针对受保护资源的多个组中的任一个的请求的互连结构来调节到窥探者的传送速率。