公开(公告)号：US08676606B1

公开(公告)日：2014-03-18

申请号：US12917061

申请日：2010-11-01

申请人： Gyula J. Nadas ,  Michael R. Johnson ,  Anthony James Fields

发明人： Gyula J. Nadas ,  Michael R. Johnson ,  Anthony James Fields

IPC分类号： G06Q50/00

CPC分类号： G06Q50/22 ,  G06F19/00 ,  G06F19/3456 ,  G06Q10/10 ,  G16H40/20

摘要： Systems and methods of providing comprehensive pharmaceutical consultations are disclosed, including generating a consultation recording block corresponding to a filling of a prescription order for a patient. The consultation recording block may include multiple consultation entries, where each consultation entry corresponds to a particular pharmaceutical consultation that is desired or required to occur in conjunction with the prescription fill. Input corresponding to various fields of various consultation entries may be received and stored. Different fields of different consultation entries corresponding to a particular patient and to a particular prescription order may be displayed, populated, viewed, resolved and authorized by different pharmaceutical personnel at different work flow stages of the filling, and in some cases, one or more consultation entries may be automatically generated and at least partially automatically populated. The techniques described herein allow for more comprehensive pharmaceutical consultations as compared to presently known techniques.

摘要翻译： 公开了提供综合性药物咨询的系统和方法，包括生成与填充患者的处方顺序相对应的咨询记录块。 咨询记录块可以包括多个咨询条目，其中每个咨询条目对应于期望或需要与处方填充一起发生的特定药物咨询。 可以接收并存储与各种咨询条目的各个领域相对应的输入。 在不同的工作流程阶段，不同的药剂人员在不同的工作流程阶段可以显示，填充，查看，解决和授权与特定患者和特定处方顺序相对应的不同咨询条目的不同领域，并且在一些情况下，一个或多个咨询 条目可能会自动生成，至少部分自动填充。 与目前已知的技术相比，本文描述的技术允许更全面的药物咨询。

公开(公告)号：US20090284126A1

公开(公告)日：2009-11-19

申请号：US12258107

申请日：2008-10-24

申请人： Jonathan Michael PROTZ ,  Maarc Stephen Verdiel ,  David James Fields

发明人： Jonathan Michael PROTZ ,  Maarc Stephen Verdiel ,  David James Fields

IPC分类号： H01J63/04

CPC分类号： H01J25/10

摘要： The present invention relates to the formation of a vacuum electronics circuit by the fusion bonding of multiple substrate wafers, e.g., silicon, copper, or other suitable conductive material, each etched using DRIE, cut using EDM, or machined by other suitable means. Other aspects of the invention relate to the alignment of a cathode with tube by fusion bonding the cathode wafer to a tube built using the fabrication methods described herein. Yet other aspects involve the alignment of dies or wafers during the fabrication of a vacuum electronics device using the “lego” technique outlined herein. In yet other aspects, fabrication methods are described.

摘要翻译： 本发明涉及通过多个衬底晶片（例如硅，铜或其它合适的导电材料）的熔接来形成真空电子电路，每个衬底晶片使用DRIE蚀刻，使用EDM切割，或者由其它合适的方法加工。 本发明的其它方面涉及通过将阴极晶片与使用本文所述的制造方法构建的管子进行熔接将阴极与管线对准。 还有其它方面涉及使用本文概述的“lego”技术在制造真空电子设备期间对准晶片或晶片。 在其它方面，描述了制造方法。

公开(公告)号：US20080046651A1

公开(公告)日：2008-02-21

申请号：US11923952

申请日：2007-10-25

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  Bradley McCredie ,  William Starke

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  Bradley McCredie ,  William Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/127

摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。 在替代实施例中，利用直接干预来访问相同级别的受害者缓存。

公开(公告)号：US20080040556A1

公开(公告)日：2008-02-14

申请号：US11835984

申请日：2007-08-08

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

公开(公告)号：US20070266126A1

公开(公告)日：2007-11-15

申请号：US11279643

申请日：2006-04-13

申请人： Leo Clark ,  James Fields ,  Benjiman Goodman ,  William Starke ,  Jeffrey Stuecheli

发明人： Leo Clark ,  James Fields ,  Benjiman Goodman ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F15/173

CPC分类号： G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.

摘要翻译： 数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送 处理单位。 该通信包括具有请求的操作和表示对请求的系统响应的组合响应。 至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列 在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。 票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

公开(公告)号：US20070061630A1

公开(公告)日：2007-03-15

申请号：US11225639

申请日：2005-09-13

申请人： James Fields ,  Benjiman Goodman ,  Praveen Reddy

发明人： James Fields ,  Benjiman Goodman ,  Praveen Reddy

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/076 ,  G06F11/0793

摘要： A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

摘要翻译： 一种用于从数据处理系统中的挂起状态恢复的数据处理系统，方法和计算机可用介质。 数据处理系统包括耦合处理单元的集合。 处理单元包括诸如两个或更多个处理核心的处理单元组件的集合，以及高速缓存阵列，处理器核心主控器，高速缓存侦听器和本地挂起管理器。 本地挂起管理器确定处理单元组件的集合中的至少一个组件是否已进入挂起状态。 如果本地挂起管理器确定至少有一个组件已进入挂起状态，则节流管理器会阻止处理单元的性能，以试图将至少一个组件从挂起状态中断。

公开(公告)号：US20070022250A1

公开(公告)日：2007-01-25

申请号：US11184343

申请日：2005-07-19

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Phillip Williams

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Phillip Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/126 ,  G06F2212/1032

摘要： A system and method of responding to a cache read error with a temporary cache directory column delete. A read command is received at a cache controller. In response to determining that data requested by said read command is stored in a specific data location in the cache, a read of the data is initiated. In response to determining the read of said data results in an error, a column delete indicator for an associativity class including a specific data location to temporarily prevent allocation within the associativity class of storage locations is set. A specific line delete command that marks the specific data location as deleted is issued. In response to the issuing of the specific line delete command, the column delete indicator for the associativity class, such that storage locations within the associativity class other than the specific data location can again be allocated to hold new data is set.

摘要翻译： 使用临时高速缓存目录列删除来响应缓存读取错误的系统和方法。 在高速缓存控制器处接收读命令。 响应于确定由所述读取命令请求的数据被存储在高速缓存中的特定数据位置中，开始读取数据。 响应于确定所述数据的读取导致错误，设置用于包括特定数据位置的关联性类的列删除指示符，以临时阻止存储位置的关联性类别内的分配。 发出将特定数据位置标记为已删除的特定行删除命令。 响应于发出特定行删除命令，设置关联性类的列删除指示符，使得可以再次分配除特定数据位置之外的关联性类中的存储位置以保存新数据。

公开(公告)号：US20060187818A1

公开(公告)日：2006-08-24

申请号：US11054288

申请日：2005-02-09

申请人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

发明人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

IPC分类号： H04J1/16

CPC分类号： G06F11/0793 ,  G06F11/0724

摘要： A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

摘要翻译： 本发明提供了一种方法，装置和计算机指令，以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功，则将第二个测试命令发送到所有处理器或其他节点，如果节点被删除。 如果第二个命令成功，则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时，控制逻辑将恢复到当前模式寄存器的值，并发送第三个测试命令来检查错误。 如果遇到错误，致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误，则使用先前配置的拓扑恢复系统操作。

公开(公告)号：US20060184706A1

公开(公告)日：2006-08-17

申请号：US11055847

申请日：2005-02-11

申请人： James Fields ,  Michael Floyd ,  Paul Lecocq

发明人： James Fields ,  Michael Floyd ,  Paul Lecocq

IPC分类号： G06F13/14

CPC分类号： G06F13/1652 ,  Y10S370/916

摘要： The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes pervasive command bandwidth while the use of the functional bus minimizes the number of interchip connections.

公开(公告)号：US20060179272A1

公开(公告)日：2006-08-10

申请号：US11055297

申请日：2005-02-10

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F15/00

CPC分类号： G06F13/385 ,  G06F9/546

摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.

摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个 处理单位。 互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。 互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应 响应。