公开(公告)号：US20210183909A1

公开(公告)日：2021-06-17

申请号：US17186424

申请日：2021-02-26

Applicant: Japan Display Inc.

Inventor： Koji YAMAMOTO ,  Tatsuya Ishii

IPC: H01L27/12 ,  G09G3/36 ,  H01L29/786 ,  H01L27/02 ,  G09G3/3266

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US11521571B2

公开(公告)日：2022-12-06

申请号：US17480754

申请日：2021-09-21

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa ,  Tatsuya Ishii

IPC: G09G3/36 ,  G09G3/00

Abstract: According to one embodiment, a display device including a plurality of pixels each of which includes a memory is provided. The display device includes a plurality of signal lines connected to the plurality of pixels, a signal line drive circuit configured to provide a data signal to one of the memories through one of the signal lines, a readout circuit configured to read the data signal in the memory through the signal line, and an output wire configured to externally output the data signal read by the readout circuit without passing through the signal line drive circuit.

公开(公告)号：US11282870B2

公开(公告)日：2022-03-22

申请号：US17186424

申请日：2021-02-26

Applicant: Japan Display inc.

Inventor： Koji Yamamoto ,  Tatsuya Ishii

IPC: G09G5/00 ,  H01L27/12 ,  G09G3/36 ,  H01L29/786 ,  H01L27/02 ,  G09G3/3266

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US10665621B2

公开(公告)日：2020-05-26

申请号：US16558850

申请日：2019-09-03

Applicant: Japan Display Inc.

Inventor： Koji Yamamoto ,  Tatsuya Ishii

IPC: G09G5/00 ,  H01L27/12 ,  G09G3/36 ,  H01L29/786 ,  H01L27/02 ,  G09G3/3266

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US10446588B2

公开(公告)日：2019-10-15

申请号：US16196269

申请日：2018-11-20

Applicant: Japan Display Inc.

Inventor： Koji Yamamoto ,  Tatsuya Ishii

IPC: G09G5/00 ,  H01L27/12 ,  G09G3/3266 ,  G09G3/36 ,  H01L27/02 ,  H01L29/786

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US10163943B2

公开(公告)日：2018-12-25

申请号：US15912672

申请日：2018-03-06

Applicant: Japan Display Inc.

Inventor： Koji Yamamoto ,  Tatsuya Ishii

IPC: G09G5/00 ,  H01L27/12 ,  G09G3/3266 ,  G09G3/36 ,  H01L27/02 ,  H01L29/786

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.