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11.发明授权Enhanced verification through binary decision diagram-based target decomposition 有权通过基于二进制决策图的目标分解来增强验证公开(公告)号：US07921394B2
公开(公告)日：2011-04-05
申请号：US11952535
申请日：2007-12-07
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.
摘要翻译： 公开了一种用于执行电子设计验证的方法，系统和计算机程序产品。 该方法包括接收包括第一目标组，主要输入集和包括一个或多个寄存器的第一寄存器组的设计。 生成设计的二进制决策图分析。 使用第一目标集合和主要输入集合的二进制判定图分析来生成所选寄存器的一个或多个下一个状态的递归提取。 递归提取被分解以产生第二目标集合，并且验证第二目标集合。
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12.发明授权Reduction of XOR/XNOR subexpressions in structural design representations 有权在结构设计表示中减少XOR / XNOR子表达式公开(公告)号：US07913218B2
公开(公告)日：2011-03-22
申请号：US11955152
申请日：2007-12-12
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于在结构设计表示中减少XOR / XNOR子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含XOR门的电子电路。 从一组适用的简化模式中选择用于初始设计的第一简化模式，其中第一简化模式是XOR / XNOR简化模式，并且根据第一简化模式执行简化初始设计以生成缩减 设计包含减少数量的异或门。 确定缩减设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为 减少设计。
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13.发明授权Enhanced verification through binary decision diagram-based target decomposition using state analysis extraction 有权通过使用状态分析提取的二进制决策图目标分解来增强验证公开(公告)号：US07908575B2
公开(公告)日：2011-03-15
申请号：US11848356
申请日：2007-08-31
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.
摘要翻译： 公开了一种用于执行电子设计验证的方法，系统和计算机程序产品。 该方法包括接收包括第一目标组，主要输入集和包括一个或多个寄存器的第一寄存器组的设计。 生成设计的二进制决策图分析。 使用第一目标集合和主要输入集合的二进制判定图分析来生成所选寄存器的一个或多个下一个状态的递归提取。 递归提取被分解以产生第二目标集合，并且验证第二目标集合。
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14.发明申请Computer Program Product for Extending Incremental Verification of Circuit Design to Encompass Verification Restraints 失效计算机程序产品用于扩展电路设计的增量验证以涵盖验证约束公开(公告)号：US20090049416A1
公开(公告)日：2009-02-19
申请号：US12180533
申请日：2008-07-26
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.
摘要翻译： 增量验证方法包括消除来自第一网表的验证约束并且使用所得到的网表来创建适合于确定设计的第一网表与第二网表之间的等价性的无约束复合网表。 从网表中消除约束可以包括在原始约束为FALSE的任何周期之后添加修改的约束网络，其中修改的约束网络对于所有周期是假的。 该方法可以包括，而不是消除约束，确定验证结果是目标未被断言的结果，并且第二网表约束是第一网表约束的超集，或者验证结果是目标断言结果， 第一个网表约束是第二个网表限制的超集。 在任一情况下，该方法可以包括通过将所有原始约束导入到复合网表中来创建复合网表。
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15.发明授权Method and system for reduction of XOR/XNOR subexpressions in structural design representations 失效在结构设计表示中减少XOR / XNOR子表达式的方法和系统公开(公告)号：US07340694B2
公开(公告)日：2008-03-04
申请号：US11086720
申请日：2005-03-22
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于在结构设计表示中减少XOR / XNOR子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含XOR门的电子电路。 从一组适用的简化模式中选择用于初始设计的第一简化模式，其中第一简化模式是XOR / XNOR简化模式，并且根据第一简化模式执行简化初始设计以生成缩减 设计包含减少数量的异或门。 确定缩减设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为 减少设计。
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16.发明授权Incremental design reduction via iterative overapproximation and re-encoding strategies 有权通过迭代过度近似和重新编码策略来减少增量设计公开(公告)号：US07930672B2
公开(公告)日：2011-04-19
申请号：US12027085
申请日：2008-02-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.
摘要翻译： 公开了一种逐渐减小设计的方法。 逻辑验证工具接收与设计相关的设计和属性，然后选择用于减少设计的多种不同技术中的一种或多种。 然后，逻辑验证工具减少设计，以使用一种或多种技术创建减少的设计，并尝试在减少的设计上为属性生成有效的解决方案。 逻辑验证工具确定是否生成了一个有效的解决方案，如果没有生成解决方案，则会使用缩减的设计替换设计。 在生成有效的解决方案之前，逻辑验证工具迭代地执行选择，减少，确定和替换步骤。
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17.发明授权Method and system for reduction of and/or subexpressions in structural design representations 有权在结构设计表示中减少和/或次表达的方法和系统公开(公告)号：US07823093B2
公开(公告)日：2010-10-26
申请号：US11944663
申请日：2007-11-26
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于减少包含AND和OR门的结构设计表示中的子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含与门的电子电路。 选择用于从一组适用的简化模式进行初始设计的第一简化模式，其中所述简化模式是AND / OR简化模式，并且执行根据第一简化模式的初始设计的简化以生成缩减设计 。 确定减小设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为简化的设计 。
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18.发明授权Computer program product for extending incremental verification of circuit design to encompass verification restraints 失效计算机程序产品，用于扩展电路设计的增量验证，以涵盖验证限制公开(公告)号：US07779378B2
公开(公告)日：2010-08-17
申请号：US12180533
申请日：2008-07-26
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.
摘要翻译： 增量验证方法包括消除来自第一网表的验证约束并且使用所得到的网表来创建适合于确定设计的第一网表与第二网表之间的等价性的无约束复合网表。 从网表中消除约束可以包括在原始约束为FALSE的任何周期之后添加修改的约束网络，其中修改的约束网络对于所有周期是假的。 该方法可以包括，而不是消除约束，确定验证结果是目标未被断言的结果，并且第二网表约束是第一网表约束的超集，或者验证结果是目标断言结果， 第一个网表约束是第二个网表限制的超集。 在任一情况下，该方法可以包括通过将所有原始约束导入到复合网表中来创建复合网表。
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19.发明申请System and Program Product for Incremental Design Reduction via Iterative Overapproximation and Re-Encoding Strategies 有权系统和程序产品通过迭代过近似和重新编码策略减少增量设计公开(公告)号：US20080127002A1
公开(公告)日：2008-05-29
申请号：US12027085
申请日：2008-02-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.
摘要翻译： 公开了一种逐渐减小设计的方法。 逻辑验证工具接收与设计相关的设计和属性，然后选择用于减少设计的多种不同技术中的一种或多种。 然后，逻辑验证工具减少设计，以使用一种或多种技术创建减少的设计，并尝试在减少的设计上为属性生成有效的解决方案。 逻辑验证工具确定是否生成了一个有效的解决方案，如果没有生成解决方案，则会使用缩减的设计替换设计。 在生成有效的解决方案之前，逻辑验证工具迭代地执行选择，减少，确定和替换步骤。
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20.发明授权Method for incremental design reduction via iterative overapproximation and re-encoding strategies 有权通过迭代过近似和重新编码策略减少增量设计的方法公开(公告)号：US07370292B2
公开(公告)日：2008-05-06
申请号：US11011246
申请日：2004-12-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.
摘要翻译： 公开了一种逐渐减小设计的方法。 逻辑验证工具接收与设计相关的设计和属性，然后选择用于减少设计的多种不同技术中的一种或多种。 然后，逻辑验证工具减少设计，以使用一种或多种技术创建减少的设计，并尝试在减少的设计上为属性生成有效的解决方案。 逻辑验证工具确定是否生成了一个有效的解决方案，如果没有生成解决方案，则会使用缩减的设计替换设计。 在生成有效的解决方案之前，逻辑验证工具迭代地执行选择，减少，确定和替换步骤。
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