公开(公告)号：US07601630B2

公开(公告)日：2009-10-13

申请号：US11020827

申请日：2004-12-22

申请人： Je-Min Park ,  Dong-Won Shin ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Dong-Won Shin ,  Yoo-Sang Hwang

IPC分类号： H01L21/4763 ,  H01L21/8239 ,  H01L21/8242

CPC分类号： H01L21/76895 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed therein, and forming both a first landing pad in the core region on the insulation layer and a second landing pad in the peripheral region, the first landing pad being overlapped with a part of a first conductive line. The invention reduces the contact resistance and prevents or minimizes a device failure caused by a misalignment, with the simplified process.

摘要翻译： 制造半导体存储器件的方法和形成电阻器和蚀刻保护层的结构以降低接触电阻。 根据本发明的制造半导体存储器件的方法包括在具有单元阵列区域，芯区域和周边区域的半导体衬底上形成绝缘层，每个晶体管阵列区域和外围区域都具有形成在其中的至少一个晶体管，并且形成第一 在绝缘层上的芯区域中的着陆焊盘和外围区域中的第二着陆焊盘，第一着陆焊盘与第一导电线的一部分重叠。 本发明通过简化的过程降低了接触电阻并且防止或最小化由不对准引起的设备故障。

公开(公告)号：US20070259494A1

公开(公告)日：2007-11-08

申请号：US11780026

申请日：2007-07-19

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/8234 ,  H01L21/4763

CPC分类号： H01L28/20 ,  H01L21/76838 ,  H01L27/0629

摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

摘要翻译： 形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间 导电层和绝缘层。 此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。 可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。 在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分 以前暴露在洞里。

公开(公告)号：US06977197B2

公开(公告)日：2005-12-20

申请号：US10884040

申请日：2004-07-02

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

摘要： The present invention discloses a semiconductor device, comprising: bit line landing pads formed over a semiconductor substrate; storage landing pads formed on both sides of the bit line landing pads; a bit line interlayer insulator formed over the whole surface of the semiconductor substrate having the landing pads; a plurality of parallel bit line patterns arranged on the bit line interlayer insulator; bit line insulating layer patterns filling in gate regions between the bit line patterns; upper contact holes formed in the bit line insulating layer patterns to expose side walls of the bit line patterns and located higher than upper surfaces of the bit line patterns; contact hole spacers covering the side walls of the upper contact holes; lower contact holes penetrating the bit line insulating layer patterns and the bit line interlayer insulator below holes surrounded by the contact hole spacers to expose the storage node landing pads and self-alighed with the upper contact holes; and storage node contact plugs filling in the upper and lower contact holes.

摘要翻译： 本发明公开了一种半导体器件，包括：形成在半导体衬底上的位线着色焊盘; 存储着陆垫形成在位线着陆垫的两侧; 形成在具有着色焊盘的半导体衬底的整个表面上的位线层间绝缘体; 布置在位线层间绝缘体上的多个并行位线图案; 填充在位线图案之间的栅极区域中的位线绝缘层图案; 形成在位线绝缘层图案中的上接触孔暴露位线图案的侧壁并且位于比位线图案的上表面高; 覆盖上接触孔的侧壁的接触孔间隔件; 穿过位线绝缘层图案的下接触孔和由接触孔间隔件包围的孔下方的位线层间绝缘体暴露存储节点着陆焊盘并与上接触孔自称; 以及填充上，下接触孔的存储节点接触塞。

公开(公告)号：US20060205141A1

公开(公告)日：2006-09-14

申请号：US11364635

申请日：2006-02-27

申请人： Je-Min Park ,  Yoo-Sang Hwang ,  Seok-Soon Song

发明人： Je-Min Park ,  Yoo-Sang Hwang ,  Seok-Soon Song

IPC分类号： H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10817

摘要： A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.

摘要翻译： 一种方法包括在半导体衬底上形成下电介质层，形成位线着陆焊盘和穿透下电介质层的存储着陆焊盘，覆盖下电介质层，位线着陆焊盘和存储着陆焊盘 中间介电层，在中间介电层上形成上电介质层，部分地去除上电介质层和中间电介质层，以形成暴露存储着陆焊盘和下电介质层的一部分的接触开口，形成接触间隔物 在接触开口的内壁上，并用接触塞填充接触开口，接触插塞的顶表面大于接触插塞的与储存着陆垫接触的表面，触头顶表面 相对于存储着陆垫插头偏心。

公开(公告)号：US20060113633A1

公开(公告)日：2006-06-01

申请号：US11154922

申请日：2005-06-16

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L29/00

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10894 ,  H01L28/91

摘要： A semiconductor memory device comprises a cell capacitor having a first buried contact connected with a semiconductor substrate of a cell region and a first storage node connected with the first buried contact, and a decoupling capacitor for reducing a coupling noise, having a plurality of second buried contacts formed on a semiconductor substrate portion adjacent in the cell region and extended in parallel with each other and a plurality of second storage nodes connected with the second buried contacts.

摘要翻译： 半导体存储器件包括具有与单元区域的半导体衬底连接的第一埋入触点和与第一埋入触点连接的第一存储节点的单元电容器，以及用于降低耦合噪声的去耦电容器，具有多个第二埋入 形成在与单元区域相邻并且彼此平行延伸的半导体衬底部分上的触点以及与第二埋入触点连接的多个第二存储节点。

公开(公告)号：US20050003646A1

公开(公告)日：2005-01-06

申请号：US10884040

申请日：2004-07-02

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L23/48

CPC分类号： H01L28/91 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

摘要： A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patternsare disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.

摘要翻译： 半导体器件包括位线着陆焊盘和设置在覆盖衬底的位线着色焊盘的两侧上的存储着陆焊盘。 位线层间绝缘层覆盖位线和存储着陆焊盘。 多个位线图案设置在位线层间绝缘层上。 位线图案各自包括位线和位线覆盖层图案。 线绝缘层图案被放置在位线层间绝缘层的顶表面上。 上接触孔位于位线图案之间的区域中，高于位线的上表面。 接触孔间隔件覆盖上接触孔的侧壁。 下接触孔与上接触孔自对准并延伸穿过线绝缘层图案和位线层间绝缘层，从而暴露存储节点着陆焊盘。

公开(公告)号：US07262108B2

公开(公告)日：2007-08-28

申请号：US10961896

申请日：2004-10-08

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/20

CPC分类号： H01L28/20 ,  H01L21/76838 ,  H01L27/0629

摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

摘要翻译： 形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间 导电层和绝缘层。 此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。 可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。 在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分 以前暴露在洞里。

公开(公告)号：US07176552B2

公开(公告)日：2007-02-13

申请号：US11154922

申请日：2005-06-16

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L29/00

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10894 ,  H01L28/91

摘要： A semiconductor memory device comprises a cell capacitor having a first buried contact connected with a semiconductor substrate of a cell region and a first storage node connected with the first buried contact, and a decoupling capacitor for reducing a coupling noise, having a plurality of second buried contacts formed on a semiconductor substrate portion adjacent in the cell region and extended in parallel with each other and a plurality of second storage nodes connected with the second buried contacts.

摘要翻译： 半导体存储器件包括具有与单元区域的半导体衬底连接的第一埋入触点和与第一埋入触点连接的第一存储节点的单元电容器，以及用于降低耦合噪声的去耦电容器，具有多个第二埋入 形成在与单元区域相邻并且彼此平行延伸的半导体衬底部分上的触点以及与第二埋入触点连接的多个第二存储节点。

公开(公告)号：US07078292B2

公开(公告)日：2006-07-18

申请号：US10875004

申请日：2004-06-22

申请人： Je-Min Park ,  Yoo-Sang Hwang ,  Cheol-Ju Yun

发明人： Je-Min Park ,  Yoo-Sang Hwang ,  Cheol-Ju Yun

IPC分类号： H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10814 ,  H01L28/91

摘要： A storage node contact forming method and structure reduces the number of processes required by the conventional art and increases a critical dimension of a storage node to prevent a leaning phenomenon and reduce a manufacturing cost of semiconductor memory devices. The method includes preparing a semiconductor substrate that involves at least one contact pad contacted with an active region of a memory cell transistor through an insulation layer. The method also includes forming a storage node contact of T-shape, the storage node contact being composed of a lower region contacted with an upper part of the contact pad, and an upper region that is extended to a gate length direction of the memory cell transistor and that is formed as a size larger than a size of the lower region, in order to electrically connect the contact pad with a storage node to be formed in a later process.

摘要翻译： 存储节点接触形成方法和结构减少了传统技术所需的处理次数，并且增加了存储节点的临界尺寸以防止倾斜现象并降低半导体存储器件的制造成本。 该方法包括制备半导体衬底，其包括通过绝缘层与存储单元晶体管的有源区接触的至少一个接触焊盘。 该方法还包括形成T形的存储节点接触，所述存储节点接触由与所述接触焊盘的上部接触的下部区域和延伸到所述存储单元的栅极长度方向的上部区域 晶体管，并且形成为大于下部区域的尺寸的尺寸，以便将接触焊盘与要在稍后的工艺中形成的存储节点电连接。

公开(公告)号：US20060040454A1

公开(公告)日：2006-02-23

申请号：US11252963

申请日：2005-10-17

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/331

CPC分类号： H01L28/91 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

摘要： A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patterns are disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.

摘要翻译： 半导体器件包括位线着陆焊盘和设置在覆盖衬底的位线着色焊盘的两侧上的存储着陆焊盘。 位线层间绝缘层覆盖位线和存储着陆焊盘。 多个位线图案设置在位线层间绝缘层上。 位线图案各自包括位线和位线覆盖层图案。 线绝缘层图案被放置在位线层间绝缘层的顶表面上。 上接触孔位于位线图案之间的区域中，高于位线的上表面。 接触孔间隔件覆盖上接触孔的侧壁。 下接触孔与上接触孔自对准并延伸穿过线绝缘层图案和位线层间绝缘层，从而暴露存储节点着陆焊盘。