公开(公告)号：US06896822B2

公开(公告)日：2005-05-24

申请号：US10321342

申请日：2002-12-16

申请人： David T. Amm ,  Jahja Trisnadi ,  James Hunter ,  Christopher Gudeman ,  Dinesh Maheshwari

发明人： David T. Amm ,  Jahja Trisnadi ,  James Hunter ,  Christopher Gudeman ,  Dinesh Maheshwari

IPC分类号： G02B5/18 ,  G02B26/08 ,  B29D11/00 ,  H01L21/00

CPC分类号： G02B26/0808

摘要： A light modulator includes elongated elements arranged parallel to each other. In a first diffraction mode, the light modulator operates to diffract an incident light into at least two diffraction orders. In a second diffraction mode, the light modulator operates to diffract the incident light into a single diffraction order. Each of the elongated elements comprises a blaze profile, which preferably comprises a reflective stepped profile across a width of each of the elongated elements and which produces an effective blaze at a blaze angle. Alternatively, the blaze profile comprises a reflective surface angled at the blaze angle. Each of selected ones of the elongated elements comprise a first conductive element. The elongated elements produce the first diffraction when a first electrical bias is applied between the first conductive elements and a substrate. A relative height of the blazed portions are adjusted to produce the second diffraction when a second electrical bias is applied between the first conductive elements and the substrate. In an alternative embodiment, each of the elongated elements includes the first conductive element and multiple elongated elements are arranged in groupings, where each of the groupings includes at least three of the elongated elements. When the multiple elongated elements are at a first height, the incident light reflects from the elongated elements. When relative heights of the multiple elongated elements are adjusted by applying individual electrical biases between the first conductive elements and the substrate, the incident light diffracts into the single diffraction order.

摘要翻译： 光调制器包括彼此平行布置的细长元件。 在第一衍射模式中，光调制器用于将入射光衍射为至少两个衍射级。 在第二衍射模式中，光调制器操作以将入射光衍射成单个衍射级。 每个细长元件包括火焰型材，其优选地包括穿过每个细长元件的宽度的反射阶梯型面，并且在火焰角度产生有效的火焰。 或者，火焰轮廓包括在火焰角度处成角度的反射表面。 细长元件中的每一个都包括第一导电元件。 当在第一导电元件和衬底之间施加第一电偏压时，细长元件产生第一衍射。 当在第一导电元件和基板之间施加第二电偏压时，调整闪耀部分的相对高度以产生第二衍射。 在替代实施例中，每个细长元件包括第一导电元件，并且多个细长元件被分组地布置，其中每个组包括至少三个细长元件。 当多个细长元件处于第一高度时，入射光从细长元件反射。 当通过在第一导电元件和衬底之间施加单独的电偏压来调节多个细长元件的相对高度时，入射光衍射成单个衍射级。

公开(公告)号：US06829077B1

公开(公告)日：2004-12-07

申请号：US10377936

申请日：2003-02-28

申请人： Dinesh Maheshwari

发明人： Dinesh Maheshwari

IPC分类号： G02B2600

CPC分类号： G02B26/0808

摘要： A light modulator includes elongated elements and a support structure. The elongated elements are arranged in parallel. Each element includes a light reflective planar surface with the light reflective planar surfaces lying in one or more parallel planes. The support structure is coupled to the elongated elements to maintain a position of the elongated elements relative to each other and to enable movement of each elongated element between a first modulator configuration and a second modulator configuration. In the first modulator configuration, the elongated elements act to reflect an incident light as a plane mirror. In the second modulator configuration, selected groups of elements are deflected and act to diffract the incident light along one or more of a plurality of diffraction planes. The groups of elements are configured according to one of a plurality of selectable group configurations. Each group configuration corresponds to one of the plurality of diffraction planes.

摘要翻译： 光调制器包括细长元件和支撑结构。 细长元件平行布置。 每个元件包括光反射平面，光反射平面位于一个或多个平行平面中。 支撑结构耦合到细长元件以保持细长元件相对于彼此的位置，并且使得能够在第一调制器配置和第二调制器配置之间移动每个细长元件。 在第一调制器配置中，细长元件用于将入射光反射为平面镜。 在第二调制器配置中，所选择的元件组被偏转并用于沿着多个衍射平面中的一个或多个衍射入射光。 元件组根据多个可选择的组配置中的一个进行配置。 每个组配置对应于多个衍射平面中的一个。

公开(公告)号：US5974508A

公开(公告)日：1999-10-26

申请号：US947188

申请日：1997-10-08

申请人： Dinesh Maheshwari

发明人： Dinesh Maheshwari

IPC分类号： G06F12/12

CPC分类号： G06F12/126 ,  G06F2212/2515

摘要： A cache memory system has a plurality of cache entries for storing memory items staged from a memory. The cache memory system locks entries so that memory items stored therein are prevented from being replaced by newly staged memory items. Entries can be locked globally whereby more than one entry is locked. Entries can also be locked locally whereby only selected ones of the entries are locked. The cache memory system can also set or clear a representation in an entry representing that such entry is not to be replaced upon being selectively activated or deactivated by an auto-lock (automatic lock) signal. The representation is memory-mapped and can be set or cleared directly by an integer unit.

摘要翻译： 高速缓冲存储器系统具有多个用于存储从存储器分级的存储器项的高速缓存条目。 高速缓冲存储器系统锁定条目，使得存储在其中的存储器项被防止被新分段的存储器项替换。 条目可以在全局锁定，多个条目被锁定。 条目也可以在本地锁定，只有选定的条目被锁定。 高速缓冲存储器系统还可以设置或清除表示在通过自动锁定（自动锁定）信号被选择性地激活或去激活时该条目不被替换的条目中。 表示是内存映射的，可以通过整数单位直接设置或清除。

公开(公告)号：US09965387B1

公开(公告)日：2018-05-08

申请号：US13180337

申请日：2011-07-11

申请人： Dinesh Maheshwari

发明人： Dinesh Maheshwari

IPC分类号： G06F12/06 ,  G06F13/16

CPC分类号： G06F12/0646 ,  G06F13/1615

摘要： A memory device can include an interface comprising a plurality of control and address connections and at least one set of data connections; memory circuits comprising a plurality of storage locations randomly accessible for read and write operations in response to an address value received on the address connections; and accelerator circuits coupled to the memory circuits and configured to perform at least one predetermined operation on data stored in the memory device to generate modified data for storage within the memory circuits in response to at least one command received on the interface; wherein the at least one command is supplemental to read and write commands executable by the memory device.

公开(公告)号：US08060708B2

公开(公告)日：2011-11-15

申请号：US12790712

申请日：2010-05-28

申请人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Herve Letourneur ,  Donald W. Smith ,  Manoj Gujral

发明人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Herve Letourneur ,  Donald W. Smith ,  Manoj Gujral

IPC分类号： G06F12/00

CPC分类号： G06F13/1694 ,  G06F12/0638

摘要： A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

摘要翻译： 所公开的电路包括用于耦合到易失性存储器的电路，用于耦合到非易失性NAND闪速存储器的电路，以及电路：（i）从处理器接收易失性存储器请求，并通过访问易失性存储器来满足易失性存储器请求，以及 （ii）从处理器接收非易失性NOR闪存读取请求，并通过访问NAND闪速存储器和易失性存储器来满足NOR读取请求。 该电路还可以包括从另一个处理器接收易失性存储器请求并通过访问易失性存储器来满足来自另一个处理器的易失性存储器请求的电路，以及从其他处理器接收NAND闪存读取请求并满足NAND读取的电路 访问NAND闪存的请求。 描述包括该电路的多处理器系统，以及用于满足NOR闪存读取请求的方法。

公开(公告)号：US20100228926A1

公开(公告)日：2010-09-09

申请号：US12720525

申请日：2010-03-09

申请人： Dinesh Maheshwari

发明人： Dinesh Maheshwari

IPC分类号： G06F12/00 ,  G06F11/27

CPC分类号： G11C7/1075

摘要： An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.

摘要翻译： 集成电路设备可以包括具有访问至少一个存储器阵列的单个存储器端口的第一集成电路（IC）部分，该单个端口包括第一组地址，控制和数据路径; 以及第二IC部分，其包括至少第一存储器端口和第二存储器端口，用于通过第一IC部分的单个端口提供对第一IC部分的存储器位置的访问。

公开(公告)号：US07450409B1

公开(公告)日：2008-11-11

申请号：US11384736

申请日：2006-03-20

申请人： Dinesh Maheshwari

发明人： Dinesh Maheshwari

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A content addressable memory (CAM) device can include a plurality of CAM cells arranged in rows and columns to form multi-byte words. Each CAM cell can include a comparator circuit and one or more data storing circuits. Each comparator circuit can have one or more charge transfer paths arranged between a match line and a first voltage source node. Each data storing circuit can include a write circuit that provides a controllable impedance path between one or more charge transfer paths and a data storage node of the data storing circuit.

摘要翻译： 内容可寻址存储器（CAM）设备可以包括以行和列排列以形成多字节字的多个CAM单元。 每个CAM单元可以包括比较器电路和一个或多个数据存储电路。 每个比较器电路可以具有布置在匹配线和第一电压源节点之间的一个或多个电荷转移路径。 每个数据存储电路可以包括写入电路，其在一个或多个电荷传送路径与数据存储电路的数据存储节点之间提供可控阻抗路径。

公开(公告)号：US20080046638A1

公开(公告)日：2008-02-21

申请号：US11465698

申请日：2006-08-18

申请人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Herve Letourneur ,  Donald W. Smith ,  Manoj Gujral

发明人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Herve Letourneur ,  Donald W. Smith ,  Manoj Gujral

IPC分类号： G06F12/00

CPC分类号： G06F13/1694 ,  G06F12/0638

摘要： A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

摘要翻译： 所公开的电路包括用于耦合到易失性存储器的电路，用于耦合到非易失性NAND闪速存储器的电路，以及电路：（i）从处理器接收易失性存储器请求，并通过访问易失性存储器来满足易失性存储器请求，以及 （ii）从处理器接收非易失性NOR闪存读取请求，并通过访问NAND闪速存储器和易失性存储器来满足NOR读取请求。 该电路还可以包括从另一个处理器接收易失性存储器请求并通过访问易失性存储器来满足来自另一个处理器的易失性存储器请求的电路，以及从另一处理器接收NAND闪存读取请求并满足NAND读取 访问NAND闪存的请求。 描述包括该电路的多处理器系统，以及用于满足NOR闪存读取请求的方法。

公开(公告)号：US07298635B1

公开(公告)日：2007-11-20

申请号：US11376764

申请日：2006-03-15

申请人： Dinesh Maheshwari

发明人： Dinesh Maheshwari

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A content addressable memory (CAM) cell circuit can include a match section that enables an impedance path coupled to a match line in response to a comparison between a data value and a compare data value. At least a first storage circuit can be connected to the match section, and provides the data value on a first storage node and a complementary data value on a second storage node. At least a first bit line can be coupled to the first storage node by a first access controllable impedance path and coupled to the second storage node by a second access controllable impedance path.

摘要翻译： 内容可寻址存储器（CAM）单元电路可以包括匹配部分，其响应于数据值和比较数据值之间的比较，使得能够耦合到匹配线的阻抗路径。 至少第一存储电路可以连接到匹配部分，并且在第一存储节点上提供数据值和在第二存储节点上提供互补数据值。 至少第一位线可以通过第一访问可控阻抗路径耦合到第一存储节点，并且通过第二访问可控阻抗路径耦合到第二存储节点。

公开(公告)号：US07251147B1

公开(公告)日：2007-07-31

申请号：US11146639

申请日：2005-06-07

申请人： Dinesh Maheshwari

发明人： Dinesh Maheshwari

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C15/00

摘要： A content comparator memory (CCM) device can include a row (100) of CCM cells (102-1 to 102-I). Each CCM cell (102-1 to 102-I) can have a controllable signal path (104-1 to 104-I) arranged in series to form a match path (106) that provides a match indication MATCH that can be activated when a comparand value (CD[1:I]) is determined to match a stored data value. Each CCM cell (102-1 to 102-I) can also be commonly connected to a comparator line (110) that can provide a comparator indication CMP when a compare value (CD[1:I]) has a predetermined magnitude with respect to a stored value.

摘要翻译： 内容比较器存储器（CCM）设备可以包括CCM单元（102-1至102-I）的行（100）。 每个CCM单元（102-1至102-I）可以具有串联布置的可控信号路径（104-1至104-I），以形成匹配路径（106），该匹配路径（106）提供匹配指示MATCH，其可以在 确定比较值（CD [1：I]）以匹配存储的数据值。 每个CCM单元（102-1至102-I）也可以共同地连接到比较器线（110），当比较值（CD [1：I]）相对于 存储值。