公开(公告)号：US4644264A

公开(公告)日：1987-02-17

申请号：US717409

申请日：1985-03-29

申请人： Johannes G. Beha ,  Russell W. Dreyfus ,  Allan M. Hartstein ,  Gary W. Rubloff

发明人： Johannes G. Beha ,  Russell W. Dreyfus ,  Allan M. Hartstein ,  Gary W. Rubloff

IPC分类号： G01R31/28 ,  G01R31/308 ,  H01L21/66 ,  G01R15/12 ,  G01R31/22 ,  G01R31/26

CPC分类号： G01R31/308 ,  H01L22/14 ,  H01L2924/0002

摘要： Covering metal test pads of a passivated integrated circuit process intermediate wafer or completed integrated circuit chip-to-test, with a thin conductive overlayer, and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, provides a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated. Such a chip-to-test may be nondestructively tested in air at one or several stages of its processing, without the sacrifices of mechanical probing or of bringing test sites out to output pads. The conductive overlayer may be removed after tests have been completed. Integrated circuit process intermediate chips may be specially designed for testability, with test sites grouped for easy access through windows left uncovered by subsequent layers.

公开(公告)号：US4525730A

公开(公告)日：1985-06-25

申请号：US445331

申请日：1982-11-29

申请人： Johannes G. Beha ,  Heinz Jaeckel ,  Peter Vettiger

发明人： Johannes G. Beha ,  Heinz Jaeckel ,  Peter Vettiger

IPC分类号： H01L39/22 ,  H01L27/12 ,  H01L45/00 ,  H01L45/02

CPC分类号： H01L39/223 ,  Y10S505/874

摘要： Planar junction Josephson interferometer in which the junctions (24) are "buried" underneath the interferometer bridge (27) connecting the junction counter-electrodes (25). The insulation (26) that separates the common base electrode (22) from the bridge (27) is extended between the bridge and the upper surfaces of the counter-electrodes. This design permits, without decreasing the interferometer loop inductance, a reduction of the interferometer area and thus results in a higher packaging density in logic or memory applications.The buried junction concept can be applied in symmetric or asymmetric interferometer designs with virtually any number of junctions, any type of input current control or current feeding scheme.The interferometer can be produced using conventional evaporation, photo-resist, and etch processes based on optical lithography. Further area reduction is achieved in applying e-beam or x-ray technology.

摘要翻译： 平面接合约瑟夫森干涉仪，其中连接（24）“接地”在连接相对电极（25）的干涉仪桥（27）下方。 将公共基极（22）与桥接器（27）分离的绝缘体（26）在桥接器和对置电极的上表面之间延伸。 该设计允许在不降低干涉仪环路电感的情况下减少干涉仪面积，从而导致逻辑或存储器应用中更高的封装密度。 掩埋连接点概念可以应用于对称或非对称干涉仪设计中，具有任何数量的连接点，任何类型的输入电流控制或电流馈送方案。 干涉仪可以使用基于光学光刻的常规蒸发，光刻胶和蚀刻工艺制造。 在应用电子束或x射线技术方面实现了进一步的面积减少。