公开(公告)号：US07680988B1

公开(公告)日：2010-03-16

申请号：US11554563

申请日：2006-10-30

申请人： John R. Nickolls ,  Brett W. Coon ,  Ming Y. Siu ,  Stuart F. Oberman ,  Samuel Liu

发明人： John R. Nickolls ,  Brett W. Coon ,  Ming Y. Siu ,  Stuart F. Oberman ,  Samuel Liu

IPC分类号： G06F13/16

CPC分类号： G06F12/084 ,  G06F9/544 ,  G06F15/167 ,  Y02D10/13

摘要： A shared memory is usable by concurrent threads in a multithreaded processor, with any addressable storage location in the shared memory being readable and writeable by any of the threads. Processing engines that execute the threads are coupled to the shared memory via an interconnect that transfers data in only one direction (e.g., from the shared memory to the processing engines); the same interconnect supports both read and write operations. The interconnect advantageously supports multiple parallel read or write operations.

摘要翻译： 共享存储器可由多线程处理器中的并发线程使用，共享存储器中的任何可寻址存储位置可由任何线程读取和写入。 执行线程的处理引擎通过仅在一个方向（例如，从共享存储器到处理引擎）传送数据的互连来耦合到共享存储器; 相同的互连支持读写操作。 互连有利地支持多个并行读或写操作。

公开(公告)号：US20120221808A1

公开(公告)日：2012-08-30

申请号：US13466057

申请日：2012-05-07

申请人： Brett W. Coon ,  Ming Y. Siu ,  Weizhong Xu ,  Stuart F. Oberman ,  John R. Nickolls ,  Peter C. Mills

发明人： Brett W. Coon ,  Ming Y. Siu ,  Weizhong Xu ,  Stuart F. Oberman ,  John R. Nickolls ,  Peter C. Mills

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  Y02D10/13

摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

摘要翻译： 多线程处理器中的并发线程使用内存。 任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。 存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。 序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。 允许所有这些请求并行进行，而其他请求被推迟。 可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

公开(公告)号：US08225076B1

公开(公告)日：2012-07-17

申请号：US12233515

申请日：2008-09-18

申请人： Brett W. Coon ,  Peter C. Mills ,  Stuart F. Oberman ,  Ming Y. Siu

发明人： Brett W. Coon ,  Peter C. Mills ,  Stuart F. Oberman ,  Ming Y. Siu

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3838 ,  G06F9/3879 ,  G06F9/3885

摘要： A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction buffer, the register identifiers of the registers specified in the instruction are compared with the register identifiers stored in the scoreboard memory for that instruction's thread, and a multi-bit value representing the comparison result is generated. The multi-bit value is stored with the instruction in the instruction buffer and may be updated as instructions belonging to the same thread complete their execution. Before the instruction is issued for execution, this multi-bit value is checked. If this multi-bit value indicates that none of the registers specified in the instruction have pending writes, the instruction is allowed to issue for execution.

摘要翻译： 用于处理单元的记分板存储器具有分配给要处理的多个线程中的每一个的分离的存储器区域。 对于每个线程，记分板存储器存储具有待处理写入的寄存器的寄存器标识符。 当指令被添加到指令缓冲器中时，将指令中指定的寄存器的寄存器标识符与存储在该指令的线程的记分板存储器中的寄存器标识进行比较，并生成表示比较结果的多位值。 多位值与指令一起存储在指令缓冲器中，并且可以更新为属于同一线程的指令完成其执行。 在执行指令之前，将检查该多位值。 如果该多位值表示指令中没有指定的寄存器没有挂起写操作，则允许指令执行。

公开(公告)号：US08176265B2

公开(公告)日：2012-05-08

申请号：US13165638

申请日：2011-06-21

申请人： Brett W. Coon ,  Ming Y. Siu ,  Weizhong Xu ,  Stuart F. Oberman ,  John R. Nickolls ,  Peter C. Mills

发明人： Brett W. Coon ,  Ming Y. Siu ,  Weizhong Xu ,  Stuart F. Oberman ,  John R. Nickolls ,  Peter C. Mills

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  Y02D10/13

摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

摘要翻译： 多线程处理器中的并发线程使用内存。 任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。 存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。 序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。 允许所有这些请求并行进行，而其他请求被推迟。 可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

公开(公告)号：US08108625B1

公开(公告)日：2012-01-31

申请号：US11554546

申请日：2006-10-30

申请人： Brett W. Coon ,  Ming Y. Siu ,  Weizhong Xu ,  Stuart F. Oberman ,  John R. Nickolls ,  Peter C. Mills

发明人： Brett W. Coon ,  Ming Y. Siu ,  Weizhong Xu ,  Stuart F. Oberman ,  John R. Nickolls ,  Peter C. Mills

IPC分类号： G06F12/00

CPC分类号： G06F13/1663

摘要： Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.

摘要翻译： 多线程处理器中的并发线程共享对内存的访问，任何线程都可以访问共享内存中的任何位置。 在一个实施例中，共享存储器具有多个可独立寻址的存储体，并且可以并行地访问每个存储体的一个位置。 执行线程的并行处理引擎生成一组并行内存访问请求。 地址冲突逻辑确定请求是否可以并行满足（例如，基于银行访问约束），并将请求序列化到避免冲突所需的程度。 在一些实施例中，从共享存储器中的一个地址读取的数据可以广播到多个处理引擎。

公开(公告)号：US20110252204A1

公开(公告)日：2011-10-13

申请号：US13165638

申请日：2011-06-21

申请人： Brett W. Coon ,  Ming Y. Siu ,  Weizhong Xu ,  Stuart F. Oberman ,  John R. Nickolls ,  Peter C. Mills

发明人： Brett W. Coon ,  Ming Y. Siu ,  Weizhong Xu ,  Stuart F. Oberman ,  John R. Nickolls ,  Peter C. Mills

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  Y02D10/13

摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

摘要翻译： 多线程处理器中的并发线程使用内存。 任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。 存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。 序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。 允许所有这些请求并行进行，而其他请求被推迟。 可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

公开(公告)号：US07434032B1

公开(公告)日：2008-10-07

申请号：US11301589

申请日：2005-12-13

申请人： Brett W. Coon ,  Peter C. Mills ,  Stuart F. Oberman ,  Ming Y. Siu

发明人： Brett W. Coon ,  Peter C. Mills ,  Stuart F. Oberman ,  Ming Y. Siu

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3838 ,  G06F9/3879 ,  G06F9/3885

摘要： A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction buffer, the register identifiers of the registers specified in the instruction are compared with the register identifiers stored in the scoreboard memory for that instruction's thread, and a multi-bit value representing the comparison result is generated. The multi-bit value is stored with the instruction in the instruction buffer and may be updated as instructions belonging to the same thread complete their execution. Before the instruction is issued for execution, this multi-bit value is checked. If this multi-bit value indicates that none of the registers specified in the instruction have pending writes, the instruction is allowed to issue for execution.

摘要翻译： 用于处理单元的记分板存储器具有分配给要处理的多个线程中的每一个的分离的存储器区域。 对于每个线程，记分板存储器存储具有待处理写入的寄存器的寄存器标识符。 当指令被添加到指令缓冲器中时，将指令中指定的寄存器的寄存器标识符与存储在该指令的线程的记分板存储器中的寄存器标识进行比较，并生成表示比较结果的多位值。 多位值与指令一起存储在指令缓冲器中，并且可以更新为属于同一线程的指令完成其执行。 在执行指令之前，将检查该多位值。 如果该多位值表示指令中没有指定的寄存器没有挂起写操作，则允许指令执行。

公开(公告)号：US09058672B2

公开(公告)日：2015-06-16

申请号：US12898537

申请日：2010-10-05

申请人： John Erik Lindholm ,  Henry Packard Moreton ,  Ming Y. Siu ,  Stuart F. Oberman

发明人： John Erik Lindholm ,  Henry Packard Moreton ,  Ming Y. Siu ,  Stuart F. Oberman

IPC分类号： G06K9/32 ,  G06T3/40

CPC分类号： G06T3/4007

摘要： One embodiment of the present invention sets forth a technique controlling the pixel location at which the plane equation is evaluated. Multiple pixel offsets (dx, dy) may be specified that each define to a sub-pixel sample position. Attributes are then calculated for each sub-pixel sample position that is covered by a geometric primitive. One advantage of the technique is that anti-aliasing quality may be improved since high frequency color components may be selectively supersampled for particular geometric primitives.

摘要翻译： 本发明的一个实施例提出了一种控制平面方程被评估的像素位置的技术。 可以指定多个像素偏移（dx，dy），每个像素偏移定义为子像素采样位置。 然后对由几何图元覆盖的每个子像素样本位置计算属性。 该技术的一个优点是可以改善抗混叠质量，因为可以对特定几何基元选择性地超采样高频彩色分量。

公开(公告)号：US08533435B2

公开(公告)日：2013-09-10

申请号：US12875843

申请日：2010-09-03

申请人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

发明人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

IPC分类号： G06F9/34

CPC分类号： G06F9/3012 ,  G06F9/30098 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.

摘要翻译： 本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。 由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。 通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中 银行寄存器文件。 由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。 然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

公开(公告)号：US20110072243A1

公开(公告)日：2011-03-24

申请号：US12875843

申请日：2010-09-03

申请人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

发明人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/30098 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.

摘要翻译： 本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。 由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。 通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中 银行寄存器文件。 由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。 然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。