公开(公告)号：US20090146697A1

公开(公告)日：2009-06-11

申请号：US12137127

申请日：2008-06-11

Applicant: Jong Chern LEE

Inventor： Jong Chern LEE

IPC: H03K3/00

CPC classification number: H03K19/01707 ,  H03K19/01721 ,  H03K19/018528

Abstract: The buffer circuit includes a differential amplifier differentially amplifying a reference node corresponding to a reference voltage and an input node corresponding to the input signal by sensing a potential difference of the reference voltage and the input signal. A coupling unit couples the input signal to the reference node, making it possible to improve the operating speed of the buffer circuit and operate normally when a level of the input signal or the reference voltage becomes low.

Abstract translation: 缓冲电路包括差分放大器，通过感测参考电压和输入信号的电位差，差分放大对应于参考电压的参考节点和对应于输入信号的输入节点。 耦合单元将输入信号耦合到参考节点，使得当输入信号或参考电压的电平变低时，可以提高缓冲电路的工作速度并正常工作。

公开(公告)号：US20110242928A1

公开(公告)日：2011-10-06

申请号：US12970792

申请日：2010-12-16

Applicant: Jae Bum KO ,  Jong Chern LEE

Inventor： Jae Bum KO ,  Jong Chern LEE

IPC: G11C8/06 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C8/04

Abstract: An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.

Abstract translation: 半导体存储装置的地址延迟电路包括：控制脉冲生成单元，被配置为在输入读取写入脉冲之后产生与时钟的预定倍数相对应的时间的控制脉冲; 以及延迟单元，被配置为当输入所述控制脉冲时输出内部地址，其中所述内部地址被输入为外部地址。

公开(公告)号：US20110102066A1

公开(公告)日：2011-05-05

申请号：US12650507

申请日：2009-12-30

Applicant: Sin Hyun JIN ,  Jong Chern LEE

Inventor： Sin Hyun JIN ,  Jong Chern LEE

IPC: H03H11/40

CPC classification number: G11C5/04 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/00014

Abstract: A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips.

Abstract translation: 具有多个堆叠芯片的半导体装置包括：贯穿硅通孔（TSV），被配置为将多个芯片耦合在一起并且被配置为串联耦合到多个压降单元; 多个信号转换单元，每个信号转换单元被配置为将从多个芯片中的相应一个芯片的电压降单元输出的电压转换为数字代码信号，并将数字代码信号提供为对应的一个芯片识别信号 的多个芯片; 以及多个芯片选择信号生成单元，每个芯片选择信号生成单元被配置为将芯片识别信号与芯片选择识别信号进行比较，以生成多个芯片中相应的一个芯片的芯片选择信号。

公开(公告)号：US20110102006A1

公开(公告)日：2011-05-05

申请号：US12651066

申请日：2009-12-31

Applicant: Min Seok CHOI ,  Jong Chern LEE ,  Sang Jin Byeon ,  Young Jun KU

Inventor： Min Seok CHOI ,  Jong Chern LEE ,  Sang Jin Byeon ,  Young Jun KU

IPC: G01R31/26 ,  G01R31/3187

CPC classification number: G01R31/318513

Abstract: A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.

Abstract translation: 一种用于测试半导体装置的电路包括：测试电压施加单元，被配置为响应于测试模式信号将测试电压施加到穿硅通孔（TSV）的第一端;以及检测单元，被配置为连接到第二 结束TSV，并检测从TSV的第二端输出的电流。