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    Demodulating device, demodulating method and transmission medium
    11.
    发明授权
    Demodulating device, demodulating method and transmission medium 有权
    解调装置，解调方式和传输介质

    公开(公告)号：US06313764B1

    公开(公告)日：2001-11-06

    申请号：US09154528

    申请日：1998-09-17

    申请人： Toshiyuki Nakagawa ,  Tatsuya Narahara ,  Yoshihide Shinpuku

    发明人： Toshiyuki Nakagawa ,  Tatsuya Narahara ,  Yoshihide Shinpuku

    IPC分类号： H03M700

    CPC分类号： H03M5/145 ,  G11B20/10009 ,  G11B20/1426

    摘要： According to the present invention, in the demodulating device, demodulating method and transmitting medium, a channel bit sequence of a variable length code having a minimum run d of 1 or more was decoded to a data sequence, and a code assigned to limit the minimum run d from repeating a predetermined number of times in the channel bit sequence of the variable length code was decoded to a data sequence. Design is therefore easier from the viewpoint of clock reproduction. When all the elements in the table contain a “1” representing an edge, data can be decoded more reliably. Further, when omissions are made in the codes in the table up to d bits from the code sequence lengths of the restriction lengths, data can be decoded more reliably. Thus, a clock is stably reproduced.

    摘要翻译： 根据本发明，在解调装置中，解调方法和发送介质中，将具有1或更小的最小游程d的可变长度码的信道比特序列解码为数据序列，并且分配用于限制最小值的码 在可变长度代码的通道位序列中重复预定次数的运行d被解码为数据序列。 因此，从时钟再现的角度来看，设计更容易。 当表中的所有元素包含表示边缘的“1”时，可以更可靠地解码数据。 此外，当从限制长度的代码序列长度到D位中，在表中的代码中省略多达d位时，可以更可靠地解码数据。 因此，稳定地再现时钟。

    Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes
    18.
    发明授权
    Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes 有权
    用于将数据调制和解调为可变长度代码并向代码串提供同步信号的方法和装置

    公开(公告)号：US07046736B2

    公开(公告)日：2006-05-16

    申请号：US11088464

    申请日：2005-03-24

    申请人： Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara

    发明人： Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara

    IPC分类号： H04B14/04

    CPC分类号： G11B20/1426 ,  G11B20/1403 ,  G11B2020/1287 ,  G11B2020/1453 ,  G11B2020/1457 ,  H03M5/145 ,  H04L7/0083 ,  H04L7/041 ,  H04L7/044

    摘要： A data-demodulating apparatus for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

    摘要翻译： 一种数据解调装置，用于将具有n位基本码长的可变长度码（d，k; m，n; r）解调为具有m比特的基本数据长度的数据。 接收一串代码，并且检测到具有中断最大运行的模式的同步信号。 该模式连续重复两次，最小运行重复不超过六次。 当紧接在同步信号之前的调制码序列包括在终止表中时，同步信号的第一位为“1”，用于当期望位置在小于预定数量的可变长度码时终止代码 可用。