公开(公告)号：US20150046563A1

公开(公告)日：2015-02-12

申请号：US14386248

申请日：2013-02-13

申请人： Tomoyoshi Kobori

发明人： Tomoyoshi Kobori

IPC分类号： H04L29/12

CPC分类号： H04L61/6009 ,  G06F9/30054 ,  G06F9/3009 ,  G06F9/322

摘要： An arithmetic processing device includes a first storage for storing processing contents in a state where the processing contents are associated with addresses, a second storage for storing each of the addresses of the processing contents stored in the first storage, a holding portion, a reading portion-for successively reading the addresses stored in the second storage and outputting the read addresses to the holding portion, and an execution portion for reading the processing content corresponding to the address output from the holding portion from the first storage and executing the read processing content. When the holding portion holds no address, the holding portion temporarily holds the address read by the reading portion and outputs the held address, whereas when the holding portion holds the address, the holding portion waits for completion of the execution of the processing content by the execution portion and outputs the held address after the completion of the execution.

摘要翻译： 算术处理装置包括：第一存储器，用于在处理内容与地址相关联的状态下存储处理内容;第二存储器，用于存储存储在第一存储器中的处理内容的每个地址，保持部分，读取部分 用于连续地读取存储在第二存储器中的地址并将读取地址输出到保持部分，以及执行部分，用于从第一存储器读取与从保持部分输出的地址相对应的处理内容，并执行读取处理内容。 当保持部不保持地址时，保持部暂时保持由读取部读取的地址，并输出保持的地址，而当保持部保持地址时，保持部等待完成处理内容的执行 执行部分，并在执行完成后输出保持的地址。

公开(公告)号：US09367496B2

公开(公告)日：2016-06-14

申请号：US12528893

申请日：2008-02-28

申请人： Tomoyoshi Kobori

发明人： Tomoyoshi Kobori

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with less additional hardware to effectively use a memory.A pattern generation section 11 is provided in a DMA controller 17 and generates data of a predetermined pattern, such as a zero matrix or unit matrix, in the DMA controller when data is transferred from an external shared memory 14 to an internal memory 15. Further, transfer data read out from the external shared memory is temporarily held in a queuing section 13 for queuing. At this time, switching between the transfer data from the queuing section and predetermined pattern data is made based on the number of the transfer data.

摘要翻译： 提供DMA传送装置和DMA传输方法，其能够减少外部共享存储器和DMA控制器之间的总线上的流量，具有较少的附加硬件以有效地使用存储器。 当数据从外部共享存储器14传送到内部存储器15时，在DMA控制器17中提供模式生成部分11，并且在DMA控制器中生成诸如零矩阵或单位矩阵的预定模式的数据。 将从外部共享存储器读出的传送数据临时保存在排队部分13中进行排队。 此时，基于传送数据的数量进行来自排队部的传送数据与规定的图案数据之间的切换。

公开(公告)号：US20100106865A1

公开(公告)日：2010-04-29

申请号：US12528893

申请日：2008-02-28

申请人： Tomoyoshi Kobori

发明人： Tomoyoshi Kobori

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with less additional hardware to effectively use a memory.A pattern generation section 11 is provided in a DMA controller 17 and generates data of a predetermined pattern, such as a zero matrix or unit matrix, in the DMA controller when data is transferred from an external shared memory 14 to an internal memory 15. Further, transfer data read out from the external shared memory is temporarily held in a queuing section 13 for queuing. At this time, switching between the transfer data from the queuing section and predetermined pattern data is made based on the number of the transfer data.

摘要翻译： 提供DMA传送装置和DMA传输方法，其能够减少外部共享存储器和DMA控制器之间的总线上的流量，具有较少的附加硬件以有效地使用存储器。 当数据从外部共享存储器14传送到内部存储器15时，在DMA控制器17中提供模式生成部分11，并且在DMA控制器中生成诸如零矩阵或单位矩阵的预定模式的数据。 将从外部共享存储器读出的传送数据临时保存在排队部分13中进行排队。 此时，基于传送数据的数量进行来自排队部的传送数据与规定的图案数据之间的切换。