公开(公告)号：US09576846B2

公开(公告)日：2017-02-21

申请号：US14226770

申请日：2014-03-26

申请人： Kilho Lee

发明人： Kilho Lee

IPC分类号： H01L21/768 ,  H01L27/22

CPC分类号： H01L21/76816 ,  H01L27/228

摘要： Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.

摘要翻译： 提供了用于制造数据存储装置的方法。 一种方法可以包括在衬底上形成层间电介质层，在衬底的周边区域中形成层间电介质层以形成第一沟槽，在第一沟槽中形成第一位线，将第一位线之间的层间介质层图形化 所述外围区域形成在形成所述第一位线之后沿着所述第一沟槽延伸的第二沟槽，以及在所述第二沟槽中形成第二位线。

公开(公告)号：US06867087B2

公开(公告)日：2005-03-15

申请号：US09988183

申请日：2001-11-19

申请人： Kilho Lee ,  Woo-Tang Kang ,  Rajesh Rengarajan

发明人： Kilho Lee ,  Woo-Tang Kang ,  Rajesh Rengarajan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising:a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site;b) forming an undoped polysilicon layer over the gate oxide layer;c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer;d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions;e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; andf) affecting cooling after laser annealing to convert a-Si into polysilicon without gate oxide damage.

摘要翻译： 在制造CMOS半导体结构的双功函数栅电极的方法中，改进包括形成双功函数栅电极，使得在沟道区中不渗透硼，在栅极氧化物附近没有硼耗尽，包括： a）在nMOS位点的沟道上和pMOS位点的沟道上形成栅极氧化层; b）在栅极氧化物层上形成未掺杂的多晶硅层; c）掩蔽pMOS位点，形成a-Si层 使用第一重离子注入的nMOS位点，并将砷单独注入到a-Si层中; d）掩蔽由步骤c）形成的nMOS位点，使用第二重离子注入在pMOS位点上形成a-Si层， 并且将硼单独注入到a-Si区域中; e）在短时间内和在足以熔化至少一部分a-Si但不足以熔化多晶硅的能级下激光退火nMOS和pMOS位点; 和f）影响激光退火后的冷却，将a-Si转换为多晶硅，而不会产生栅极氧化物损伤。

公开(公告)号：US06214661B1

公开(公告)日：2001-04-10

申请号：US09489771

申请日：2000-01-21

申请人： Heon Lee ,  Young-Jin Park ,  Young Limb ,  Brian Lee ,  Kilho Lee ,  Satish Athavale ,  Jai-hoon Sim

发明人： Heon Lee ,  Young-Jin Park ,  Young Limb ,  Brian Lee ,  Kilho Lee ,  Satish Athavale ,  Jai-hoon Sim

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L27/10852 ,  H01L28/55

摘要： In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: a) preparing a bottom Pt electrode formation; b) subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; c) depositing a BSTO layer on said oxygen enriched Pt layer; d) depositing an upper Pt electrode layer on the BSTO layer; e) subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and f) depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

摘要翻译： 在形成用于DRAM器件的Pt / BSTO / Pt电容器堆叠的微电子结构的方法中，改进包括基本上消除或防止BSTO材料层的氧扩散，包括：a）制备底部Pt电极 b）使底Pt层电极形成氧气等离子体处理，在底Pt电极上形成富氧Pt层; c）在所述富氧Pt层上沉积BSTO层; d）将上Pt电极层沉积在 BSTO层; e）使上Pt电极层进行氧等离子体处理以形成掺入氧的Pt层; 以及）在配有氧的Pt层上部Pt上沉积Pt层。