公开(公告)号：US20240363652A1

公开(公告)日：2024-10-31

申请号：US18308928

申请日：2023-04-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsuan CHANG ,  Hsiu-Yun LIEN ,  Ming HUNG ,  Tung-I LIN ,  Chun CHANG ,  Chao-Ching CHANG ,  Sheng-Chan LI ,  Sheng-Chau CHEN

IPC分类号： H01L27/146

CPC分类号： H01L27/14609 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L28/75 ,  H01L28/91 ,  H01L28/92

摘要： A deep trench capacitor structure may include a metal-insulator-metal structure having an insulator layer between opposing conductive electrode layers. The deep trench capacitor structure may extend through a plurality of dielectric layers in a semiconductor device. The conductive electrode layers and the insulator layer may extend laterally into the dielectric layers. The lateral extensions of the conductive electrode layers and the insulator layer into the dielectric layers may be referred to as fin portions of the capacitor structure. The fin portions may extend laterally outward from a central portion (e.g., a trench portion) of the deep trench capacitor structure. The fin portions of the deep trench capacitor structure enable the surface area of the conductive electrode layers to be increased, which may increase the capacitance of the deep trench capacitor structure with minimal increase to the overall footprint of the deep trench capacitor structure.

公开(公告)号：US12127415B2

公开(公告)日：2024-10-22

申请号：US17606209

申请日：2021-06-08

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Xingsong Su ,  Weiping Bai ,  Mengkang Yu ,  Lianhong Wang

IPC分类号： H10K10/10 ,  H01L49/02 ,  H10B12/00

CPC分类号： H10K10/10 ,  H01L28/56 ,  H01L28/75 ,  H10B12/03

摘要： A capacitor structure includes two electrodes arranged oppositely and a dielectric layer located between the two electrodes, wherein the dielectric layer includes at least two perovskite layers stacked; an amorphous layer is provided between every two adjacent perovskite layers; two outermost perovskite layers of the at least two perovskite layers are in contact with the two electrodes, respectively.

公开(公告)号：US20240339493A1

公开(公告)日：2024-10-10

申请号：US18624808

申请日：2024-04-02

申请人： ASM IP Holding B.V.

发明人： Alessandra Leonhardt ,  Varun Sharma ,  Vivek Koladi Mootheri ,  Leo Lukose ,  Andrea Illiberi ,  Jerome Innocent ,  Aditya Chauhan

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L29/778

CPC分类号： H01L29/0607 ,  H01L21/02362 ,  H01L28/75 ,  H01L29/7786

摘要： Structures and related methods and systems for forming structures. The structures comprise a proximal contact, a distal contact, a high-k dielectric, and at least one of a proximal barrier and a distal barrier. In some embodiments, at least one of the proximal barrier and the distal barrier is constructed and arranged to inhibit Poole-Frenkel emission from the high-k dielectric when a first electric field is applied between the proximal contact and a distal contact in a first electric field direction.

公开(公告)号：US20240339491A1

公开(公告)日：2024-10-10

申请号：US18743810

申请日：2024-06-14

申请人： Taiwan Semiconductor Manfacturing Company, Ltd.

发明人： Chen-Yin HSU ,  Chun Li WU ,  Ching-Hung KAO

IPC分类号： H01G4/30

CPC分类号： H01L28/91 ,  H01L28/75

摘要： The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

公开(公告)号：US20240332348A1

公开(公告)日：2024-10-03

申请号：US18126573

申请日：2023-03-27

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YAO-HSIUNG KUNG ,  CHAO-WEN LAY

IPC分类号： H01L21/02

CPC分类号： H01L28/90 ,  H01L28/75

摘要： The present disclosure provides a memory device and a manufacturing method of the memory device. The memory device includes: a substrate, a landing area over the substrate, a bottom electrode over the landing area, and a high-k layer over the bottom electrode, wherein the bottom electrode includes a lower portion over the landing area, a middle portion over the lower portion, and an upper portion over the middle portion, and the bottom electrode has a container-shaped profile.

公开(公告)号：US20240313043A1

公开(公告)日：2024-09-19

申请号：US18675658

申请日：2024-05-28

申请人： ROHM CO., LTD.

发明人： Bungo TANAKA

IPC分类号： H01L25/16 ,  H01L23/00 ,  H01L23/14 ,  H01L29/92

CPC分类号： H01L28/75 ,  H01L23/147 ,  H01L24/32 ,  H01L24/48 ,  H01L25/162 ,  H01L28/86 ,  H01L29/92 ,  H01L2224/32235 ,  H01L2224/48248

摘要： An insulation chip includes an element insulation layer, a first capacitor, and a second capacitor. The first capacitor includes a first front surface-side electrode plate and a first back surface-side electrode plate that are disposed opposite each other. The second capacitor includes a second front surface-side electrode plate and a second back surface-side electrode plate. The second front surface-side electrode plate and the second back surface-side electrode plate are opposed to each other. In the element insulation layer, the first back surface-side electrode plate and the second back surface-side electrode plate are electrically connected. This signal transmission device includes: a first chip including a first circuit; the insulation chip; and a second chip including a second circuit configured to perform at least one of transmission and reception of a signal with the first circuit via the insulation chip.

公开(公告)号：US20240306399A1

公开(公告)日：2024-09-12

申请号：US18666498

申请日：2024-05-16

申请人： Micron Technology, Inc.

发明人： Scott J. Derner ,  Charles L. Ingalls

IPC分类号： H10B53/30 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H10B12/00 ,  H10B53/20

CPC分类号： H10B53/30 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/78 ,  H01L29/7827 ,  H10B12/00 ,  H10B53/20 ,  H01L27/0207 ,  H01L28/75

摘要： Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

公开(公告)号：US20240292595A1

公开(公告)日：2024-08-29

申请号：US18655341

申请日：2024-05-06

申请人： Winbond Electronics Corp.

发明人： Te-Hsuan Peng ,  Kai Jen

IPC分类号： H10B12/00 ,  H01L21/311 ,  H01L21/768

CPC分类号： H10B12/31 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L28/75 ,  H10B12/033

摘要： A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.

公开(公告)号：US12068364B2

公开(公告)日：2024-08-20

申请号：US17875026

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Yin Hsu ,  Chun Li Wu ,  Ching-Hung Kao

IPC分类号： H01L49/02

CPC分类号： H01L28/91 ,  H01L28/75

摘要： The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

公开(公告)号：US12054838B2

公开(公告)日：2024-08-06

申请号：US17075154

申请日：2020-10-20

申请人： Murata Manufacturing Co., Ltd. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Frédéric Voiron ,  Julien El Sabahy ,  Maxime Lemenager ,  Guy Parat

IPC分类号： C25D11/02 ,  C25D11/04 ,  C25D11/06 ,  C25D11/08 ,  C25D11/18 ,  C25D11/24 ,  C25D11/26 ,  H01L23/522 ,  H01L23/532 ,  H01L49/02

CPC分类号： C25D11/022 ,  C25D11/045 ,  C25D11/06 ,  C25D11/18 ,  H01L23/5223 ,  H01L23/53223 ,  H01L28/75

摘要： A semiconductor device that includes a porous anodic region for embedding a structure. The porous anodic region is defined by a ductile hard mask. The ductility of the hard mask reduces the potential for the hard mask to crack during the formation by anodization of the porous anodic region. The ductile hard mask may be a metal. The metal may be selected to form a stable oxide when exposed to the anodization electrolyte thereby enabling the hard mask to self-repair if a crack occurs during the anodization process.