公开(公告)号：US20220405057A1

公开(公告)日：2022-12-22

申请号：US17643697

申请日：2021-12-10

Applicant: Kioxia Corporation

Inventor： Radu BERDAN ,  Daisuke MIYASHITA ,  Jun DEGUCHI

IPC: G06F7/57 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/34

Abstract: According to one embodiment, in a semiconductor integrated circuit, the plurality of storage devices are arranged in a form of a plurality of rows. Each of the storage devices are configured to store a bit position value of a weight of multiple bits. The plurality of multiplication circuits are arranged in a form of a plurality of rows and are configured to multiply a plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results. The one or more capacitive devices are configured to accumulate charges corresponding to the plurality of multiplication results. The adder circuit are configured to generate an output voltage corresponding to the total value of the charges accumulated in the one or more capacitive devices. The plurality of input voltages have different amplitudes. Each of the input voltages is associated with a corresponding bit position of the weight.

公开(公告)号：US20220302924A1

公开(公告)日：2022-09-22

申请号：US17469374

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Radu BERDAN ,  Daisuke MIYASHITA ,  Jun DEGUCHI

IPC: H03M1/46 ,  H03M1/80 ,  G06F7/544

Abstract: According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit.