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公开(公告)号：US20230307052A1
公开(公告)日：2023-09-28
申请号：US17901239
申请日：2022-09-01
Applicant: Kioxia Corporation
Inventor： Jun DEGUCHI , Daisuke MIYASHITA , Atsushi KAWASUMI , Hidehiro SHIGA , Shinji MIYANO , Shinichi SASAKI
IPC: G11C16/08
CPC classification number: G11C16/08
Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.
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公开(公告)号：US20220309075A1
公开(公告)日：2022-09-29
申请号：US17304190
申请日：2021-06-16
Applicant: Kioxia Corporation
Inventor： Yasuto HOSHI , Daisuke MIYASHITA , Jun DEGUCHI
IPC: G06F16/25 , G06F16/242 , G06N3/04 , G06F16/245
Abstract: According to one embodiment, an information processing device includes: an encoder including a first layer and a second layer which are coupled in series; and a decoder. The encoder is configured to: generate, based on first data, a first key and a first value in the first layer, and a second key and a second value in the second layer; and generate, based on second data different from the first data, a first query in the first layer, and a second query in the second layer. The decoder is configured to: generate third data which is included in the first data and is not included in the second data, based on the first key, the first value, the first query, the second key, the second value, and the second query.
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公开(公告)号：US20220083848A1
公开(公告)日：2022-03-17
申请号：US17195775
申请日：2021-03-09
Applicant: Kioxia Corporation
Inventor： Daisuke MIYASHITA , Radu BERDAN , Yasuto HOSHI , Jun DEGUCHI
Abstract: According to an embodiment, an arithmetic device configured to execute an operation related to a neural network approximately calculates similarities between a first vector and a plurality of second vectors. Further, the arithmetic device selects, among the plurality of second vectors, a plurality of third vectors whose similarities are equal to or greater than a threshold. Furthermore, the arithmetic device also calculates similarities between the first vector and the selected plurality of third vectors.
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公开(公告)号：US20220083846A1
公开(公告)日：2022-03-17
申请号：US17198448
申请日：2021-03-11
Applicant: Kioxia Corporation
Inventor： Radu BERDAN , Daisuke MIYASHITA , Jun DEGUCHI
Abstract: According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.
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公开(公告)号：US20220076122A1
公开(公告)日：2022-03-10
申请号：US17195865
申请日：2021-03-09
Applicant: Kioxia Corporation
Inventor： Daisuke MIYASHITA , Asuka MAKI
Abstract: According to one embodiment, an arithmetic apparatus includes a non-volatile first memory, a second memory, and a controller. The first memory stores a model to be trained. The second memory has a smaller storage capacity than the first memory. The controller executes learning processing that updates a first parameter of the model based on a loss value obtained by inputting training data into the model stored in the first memory, and stores cumulative update information indicating a difference of the first parameter before and after the update in the second memory. In addition, the controller executes the learning processing using a second parameter in which the cumulative update information stored in the second memory is reflected in the first parameter read from the model stored in the first memory, and stores a difference between a third parameter obtained by updating the second parameter and the first parameter, in the second memory as the cumulative update information.
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Patent Agency Ranking
公开(公告)号：US20210089271A1
公开(公告)日：2021-03-25
申请号：US16818823
申请日：2020-03-13
Applicant: Kioxia Corporation
Inventor： Kengo NAKATA , Asuka MAKI , Daisuke MIYASHITA
Abstract: According to one embodiment, an arithmetic operation device removes a part of parameters of a predetermined number of parameters from a first model which includes the predetermined number of parameters and is trained so as to output second data corresponding to input first data and determines the number of bits of a weight parameters according to required performance related to an inference to generate a second model, and acquires data output from the second model so as to correspond to the input first data with a smaller computational complexity than the first model.
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公开(公告)号：US20230367965A1
公开(公告)日：2023-11-16
申请号：US18181642
申请日：2023-03-10
Applicant: Kioxia Corporation
Inventor： Yasuto HOSHI , Daisuke MIYASHITA , Jun DEGUCHI
IPC: G06F40/295 , G06N3/045
CPC classification number: G06F40/295 , G06N3/045
Abstract: According to one embodiment, an apparatus includes: an interface circuit configured to receive first data items respectively relating to documents and a second data item relating to a question; and a processor configured to process the first and second data items, wherein the processor is configured to: extract first named entities respectively from the first data items and extract a second named entity from the second data item; generate first vectors respectively relating to the first data items and the corresponding first named entities; generate a second vector relating to the second data item and the second named entity; calculate a similarity between each of the first vectors and the second vector; and acquire a third data item relating to an answer retrieved from the first data items based on a result of calculating the similarity.
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公开(公告)号：US20220405057A1
公开(公告)日：2022-12-22
申请号：US17643697
申请日：2021-12-10
Applicant: Kioxia Corporation
Inventor： Radu BERDAN , Daisuke MIYASHITA , Jun DEGUCHI
Abstract: According to one embodiment, in a semiconductor integrated circuit, the plurality of storage devices are arranged in a form of a plurality of rows. Each of the storage devices are configured to store a bit position value of a weight of multiple bits. The plurality of multiplication circuits are arranged in a form of a plurality of rows and are configured to multiply a plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results. The one or more capacitive devices are configured to accumulate charges corresponding to the plurality of multiplication results. The adder circuit are configured to generate an output voltage corresponding to the total value of the charges accumulated in the one or more capacitive devices. The plurality of input voltages have different amplitudes. Each of the input voltages is associated with a corresponding bit position of the weight.
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公开(公告)号：US20220302924A1
公开(公告)日：2022-09-22
申请号：US17469374
申请日：2021-09-08
Applicant: Kioxia Corporation
Inventor： Radu BERDAN , Daisuke MIYASHITA , Jun DEGUCHI
Abstract: According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit.
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公开(公告)号：US20230185529A1
公开(公告)日：2023-06-15
申请号：US17840691
申请日：2022-06-15
Applicant: Kioxia Corporation
Inventor： Radu BERDAN , Daisuke MIYASHITA , Jun DEGUCHI
Abstract: According to one embodiment, in a calculation system, a plurality of multiplying elements is arrayed to form a plurality of rows and a plurality of columns and are configured to multiply a plurality of first signals by respective weights to generate a plurality of calculation results and are configured to calculate a sum of calculation results in each column among the plurality of calculation results to generate a plurality of second signals individually for the plurality of columns. A first processing circuit is configured to receive the plurality of second signals generated by the adding elements, and to extract values corresponding to certain second signals among the plurality of second signals. A second processing circuit including a plurality of address circuits corresponding to the plurality of second signals, and configured to selectively enable address circuits corresponding to the certain second signals among the plurality of address circuits.
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