公开(公告)号：US20230185529A1

公开(公告)日：2023-06-15

申请号：US17840691

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Radu BERDAN ,  Daisuke MIYASHITA ,  Jun DEGUCHI

IPC: G06F7/523 ,  G06F7/50 ,  G06N3/063

CPC classification number: G06F7/523 ,  G06F7/50 ,  G06N3/063

Abstract: According to one embodiment, in a calculation system, a plurality of multiplying elements is arrayed to form a plurality of rows and a plurality of columns and are configured to multiply a plurality of first signals by respective weights to generate a plurality of calculation results and are configured to calculate a sum of calculation results in each column among the plurality of calculation results to generate a plurality of second signals individually for the plurality of columns. A first processing circuit is configured to receive the plurality of second signals generated by the adding elements, and to extract values corresponding to certain second signals among the plurality of second signals. A second processing circuit including a plurality of address circuits corresponding to the plurality of second signals, and configured to selectively enable address circuits corresponding to the certain second signals among the plurality of address circuits.

公开(公告)号：US20220083846A1

公开(公告)日：2022-03-17

申请号：US17198448

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Radu BERDAN ,  Daisuke MIYASHITA ,  Jun DEGUCHI

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/04

Abstract: According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

公开(公告)号：US20220083848A1

公开(公告)日：2022-03-17

申请号：US17195775

申请日：2021-03-09

Applicant: Kioxia Corporation

Inventor： Daisuke MIYASHITA ,  Radu BERDAN ,  Yasuto HOSHI ,  Jun DEGUCHI

IPC: G06N3/063 ,  G06K9/62 ,  G06F17/16 ,  G06F7/544

Abstract: According to an embodiment, an arithmetic device configured to execute an operation related to a neural network approximately calculates similarities between a first vector and a plurality of second vectors. Further, the arithmetic device selects, among the plurality of second vectors, a plurality of third vectors whose similarities are equal to or greater than a threshold. Furthermore, the arithmetic device also calculates similarities between the first vector and the selected plurality of third vectors.

公开(公告)号：US20220405057A1

公开(公告)日：2022-12-22

申请号：US17643697

申请日：2021-12-10

Applicant: Kioxia Corporation

Inventor： Radu BERDAN ,  Daisuke MIYASHITA ,  Jun DEGUCHI

IPC: G06F7/57 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/34

Abstract: According to one embodiment, in a semiconductor integrated circuit, the plurality of storage devices are arranged in a form of a plurality of rows. Each of the storage devices are configured to store a bit position value of a weight of multiple bits. The plurality of multiplication circuits are arranged in a form of a plurality of rows and are configured to multiply a plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results. The one or more capacitive devices are configured to accumulate charges corresponding to the plurality of multiplication results. The adder circuit are configured to generate an output voltage corresponding to the total value of the charges accumulated in the one or more capacitive devices. The plurality of input voltages have different amplitudes. Each of the input voltages is associated with a corresponding bit position of the weight.

公开(公告)号：US20220302924A1

公开(公告)日：2022-09-22

申请号：US17469374

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Radu BERDAN ,  Daisuke MIYASHITA ,  Jun DEGUCHI

IPC: H03M1/46 ,  H03M1/80 ,  G06F7/544

Abstract: According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit.