公开(公告)号：US06777812B2

公开(公告)日：2004-08-17

申请号：US10464591

申请日：2003-06-18

申请人： Kyu-Hyun Lee ,  Yoon-Soon Chun

发明人： Kyu-Hyun Lee ,  Yoon-Soon Chun

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of methods of fabricating protected contact plugs include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming an electrically conductive lower barrier layer that lines at least an upper portion of a sidewall of the contact hole. This lower barrier layer may comprise titanium nitride (TiN). A step is also performed to form an electrically conductive contact plug that extends in the contact hole, is electrically coupled to the lower barrier layer and protrudes above the electrically insulating layer. The contact plug may comprise tungsten (W). An electrically conductive upper barrier layer is then formed that extends on a protruded upper surface of the contact plug and on a surface of the lower barrier layer. A step may then be performed to pattern the upper barrier layer to define an electrically conductive barrier spacer that extends on a sidewall or end of the lower barrier layer and define an upper barrier layer cap on the protruded upper surface of the contact plug.

摘要翻译： 制造受保护的接触插塞的方法的实施例包括在半导体衬底上形成其中具有接触孔的电绝缘层，然后形成在接触孔的侧壁的至少上部分上的导电下阻挡层。 该下阻挡层可以包括氮化钛（TiN）。 还执行步骤以形成在接触孔中延伸的导电接触插塞，电连接到下阻挡层并突出在电绝缘层上方。 接触塞可以包括钨（W）。 然后形成导电上阻挡层，其在接触插塞的突出的上表面上延伸并且在下阻挡层的表面上延伸。 然后可以执行步骤以图案化上阻挡层以限定在下阻挡层的侧壁或端部上延伸并且在接触插塞的突出的上表面上限定上阻挡层帽的导电阻挡间隔物。

公开(公告)号：US06451651B1

公开(公告)日：2002-09-17

申请号：US09931861

申请日：2001-08-20

申请人： Byung-Jun Park ,  Kyu-Hyun Lee

发明人： Byung-Jun Park ,  Kyu-Hyun Lee

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a DRAM device comprises forming a bit line interlayer insulating layer over a substrate over which a bit line pattern is formed; planarizing the bit line interlayer insulating layer; forming enlarged grooves exposing a conductive layer of the bit line pattern; forming bit lines; forming a silicon nitride layer over the substrate; forming a silicon nitride pattern having silicon nitride spacers formed on side walls of the enlarged grooves positioned on the conductive layer; forming the bit lines at the enlarged width portions of the bit line pattern; forming storage node contacts, storage nodes, a dielectric layer, and plate electrodes at a cell area; forming a wiring interlayer insulating layer on the substrate; forming metal contact holes; and forming plugs filling the metal contact holes.

摘要翻译： 制造DRAM器件的方法包括在衬底上形成位线层间绝缘层，在其上形成位线图案; 平面化位线层间绝缘层; 形成暴露位线图案的导电层的扩大凹槽; 形成位线; 在衬底上形成氮化硅层; 形成具有形成在位于所述导电层上的所述扩大凹槽的侧壁上的氮化硅间隔物的氮化硅图案; 在位线图形的放大宽度部分形成位线; 在单元区域形成存储节点触点，存储节点，电介质层和平板电极; 在基板上形成布线层间绝缘层; 形成金属接触孔; 并形成填充金属接触孔的塞子。

公开(公告)号：US06432795B1

公开(公告)日：2002-08-13

申请号：US09705786

申请日：2000-11-06

申请人： Kyu-Hyun Lee

发明人： Kyu-Hyun Lee

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

摘要： A method of fabricating a capacitor storage node having HSG silicon on inner walls thereof, wherein the HSG silicon is formed on the inner walls of the storage node after a sacrificial insulating layer is removed, thereby increasing overall surface area of the storage node and preventing electrical bridges between adjacent storage nodes. The storage node is made of a double layer including a layer of crystallized silicon and a layer of amorphous silicon, formed in a storage opening that is formed in the sacrificial insulating layer. The crystallized silicon defines outer walls of the storage node and the amorphous silicon defines inner walls. After forming the storage node opening in the sacrificial insulating layer, crystallized silicon is formed in the opening. Amorphous silicon is then formed on the crystallized silicon. After removing the sacrificial insulating layer, HSG silicon is formed on the amorphous silicon layer.

摘要翻译： 一种制造在其内壁上具有HSG硅的电容器存储节点的方法，其中在除去牺牲绝缘层之后，在存储节点的内壁上形成HSG硅，从而增加存储节点的总表面积并防止电 相邻存储节点之间的桥接。 存储节点由形成在牺牲绝缘层中的存储开口中形成的包含结晶硅层和非晶硅层的双层构成。 结晶硅限定存储节点的外壁，非晶硅限定内壁。 在牺牲绝缘层中形成存储节点开口之后，在开口中形成结晶硅。 然后在结晶硅上形成非晶硅。 在去除牺牲绝缘层之后，在非晶硅层上形成HSG硅。

公开(公告)号：US06168992A

公开(公告)日：2001-01-02

申请号：US09181288

申请日：1998-10-28

申请人： Kyu-Hyun Lee

发明人： Kyu-Hyun Lee

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10855 ,  H01L28/91

摘要： A method for fabricating a Dynamic Random Access Memory (DRAM) device includes the steps of forming a word line on a substrate, forming a first insulating layer on the substrate and on the word line, forming a bit line the first insulating layer, and forming a second insulating layer on the first insulating layer and on the bit line. A sacrificial layer is formed on the second insulating layer, and a contact hole is formed through the sacrificial layer, and the first and second insulating layers. A conductive plug is formed in the contact hole, and the sacrificial layer is removed thereby exposing upper side portions of the conductive plug to define a capacitor electrode.

摘要翻译： 一种用于制造动态随机存取存储器（DRAM）器件的方法包括以下步骤：在衬底上形成字线，在衬底上和字线上形成第一绝缘层，形成第一绝缘层的位线，以及形成 在第一绝缘层和位线上的第二绝缘层。 牺牲层形成在第二绝缘层上，并且通过牺牲层以及第一和第二绝缘层形成接触孔。 在接触孔中形成导电插塞，去除牺牲层，从而暴露导电插塞的上侧部分以限定电容器电极。

公开(公告)号：US5990998A

公开(公告)日：1999-11-23

申请号：US829121

申请日：1997-04-10

申请人： Jae-Yong Park ,  Jae-Kyun Lee ,  Jung-Hoan Kim ,  Ki-Hyun Lyu ,  Kyu-Hyun Lee

发明人： Jae-Yong Park ,  Jae-Kyun Lee ,  Jung-Hoan Kim ,  Ki-Hyun Lyu ,  Kyu-Hyun Lee

IPC分类号： G02F1/133 ,  G02F1/1362 ,  G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/136286

摘要： A method of manufacturing an active matrix LCD is disclosed whereby gate bus lines, gate electrodes and source bus line segments are patterned from the same vacuum deposited first metal layer. An insulating layer, semiconductor layer, extrinsic semiconductor layer and second metal layer are then successively deposited on the substrate. A TFT channel region is formed by etching each of these layers in a second patterning process. During this step, storage capacitors may be formed by patterning the second metal layer so that it overlaps part of the gate bus lines. A transparent conductive layer is next deposited on the substrate. Pixel electrodes are then formed by patterning the transparent conductive layer in a third patterning process. Further, using a portion of the transparent conductive layer as a mask, the second metal layer and part of the extrinsic semiconductor layer are etched to form source and drain electrodes. Additionally, the transparent conductive layer can be patterned to provide an electrical connection between adjacent bus line segments to form a plurality of electrically continuous source bus lines.

摘要翻译： 公开了一种制造有源矩阵LCD的方法，其中栅极总线，栅电极和源极总线段被从相同的真空沉积的第一金属层图案化。 然后将绝缘层，半导体层，非本征半导体层和第二金属层依次沉积在基板上。 通过在第二图案化工艺中蚀刻这些层中的每一层来形成TFT沟道区。 在该步骤期间，可以通过对第二金属层进行图案化以使其与栅极总线的一部分重叠而形成存储电容器。 接着在衬底上沉积透明导电层。 然后通过在第三图案化工艺中图案化透明导电层来形成像素电极。 此外，使用透明导电层的一部分作为掩模，蚀刻第二金属层和非本征半导体层的一部分以形成源极和漏极。 另外，透明导电层可被图案化以在相邻的总线段之间提供电连接，以形成多个电连续的源极总线。