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公开(公告)号：US11978828B2
公开(公告)日：2024-05-07
申请号：US17467991
申请日：2021-09-07
Applicant: LG Display Co., Ltd.
Inventor： Byeong-Seong So
CPC classification number: H01L33/382 , H01L27/156 , H01L33/44 , H01L33/62 , H01Q1/243
Abstract: Embodiments of the present disclosure relate to a display panel and a display device. The display panel comprises a substrate including a first display area and a second display area each having a plurality of sub-pixels, wherein the number of sub-pixels per unit area in the first display area is less than the number of sub-pixels per unit area in the second display area; a transistor layer disposed over the substrate and including a plurality of transistors; a planarization layer over the transistor layer; a light emitting element layer including a common electrode including a plurality of holes in the first display area, disposed over the planarization layer, and including a plurality of light emitting elements; and an antenna comprising a first antenna electrode disposed in the transistor layer and a second antenna electrode disposed over the first antenna electrode, disposed in the first display area and at least a part of which overlaps the plurality of holes. In the present disclosure, the reception rate of the antenna is improved.
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公开(公告)号：US11903280B2
公开(公告)日：2024-02-13
申请号：US17979418
申请日：2022-11-02
Applicant: LG DISPLAY CO., LTD.
Inventor： Youngsung Cho , Byeong-Seong So
IPC: H10K59/131 , G09G3/3225 , G09G3/3266 , G06F3/041 , G06F3/044
CPC classification number: H10K59/131 , G06F3/0412 , G09G3/3225 , G09G3/3266 , G06F3/044 , G06F2203/04112 , G09G2300/0439 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861
Abstract: A display device includes a display panel including a plurality of subpixels and a plurality of signal lines, the display panel defining a display area having a first optical area and a normal area outside of the first optical area, and a non-display area. The first optical area includes a plurality of light emitting areas and a plurality of first transmission areas, and the normal area includes a plurality of light emitting areas. The display panel includes a plurality of first horizontal lines, among the signal lines, disposed through the first optical area. The first horizontal lines include a bypass line connected to subpixels at both boundaries of the first optical area and not connected to other subpixels inside of the first optical area, and a non-bypass line connected to the subpixels at both boundaries of the first optical area and the subpixels inside of the first optical area.
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公开(公告)号：US09620240B2
公开(公告)日：2017-04-11
申请号：US14290808
申请日：2014-05-29
Applicant: LG Display Co., Ltd.
Inventor： Byeong-Seong So , Joung-Mi Choi
CPC classification number: G11C19/28 , G09G3/3677 , G09G2310/0286
Abstract: Disclosed is a shift register including stages for sequentially outputting output pulses including carry and scan pulses. Odd-numbered stages supply corresponding scan pulses to odd-numbered gate lines in a sequential manner, and even-numbered stages supply corresponding scan pulses to even-numbered gate lines in a sequential manner. Each stage includes a carry output unit for generating a carry pulse, based on a first discharge voltage and a clock pulse having a low-level voltage equal to the first discharge voltage, and supplying the carry pulse to at least one of upstream and downstream stages, and a scan output unit for generating a scan pulse, based on a second discharge voltage having a higher voltage than the first discharge voltage and the clock pulse, and supplying the scan pulse to a corresponding gate line.
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公开(公告)号：US09418755B2
公开(公告)日：2016-08-16
申请号：US14082682
申请日：2013-11-18
Applicant: LG DISPLAY CO., LTD
Inventor： Byeong-Seong So , Seung-Ho Heo , JoungMi Choi
CPC classification number: G11C19/28 , G09G3/3266 , G09G3/3677
Abstract: Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal.
Abstract translation: 公开了一种移位寄存器和平板显示装置。 移位寄存器包括向形成在显示面板中的多个栅极线提供栅极导通电压脉冲的多个级。 每个级包括上拉晶体管，其被配置为根据第一节点的电压将多个时钟信号中的一个提供给输出节点，被配置为向输出节点提供栅极截止电压的下拉晶体管 根据第二节点的电压，被配置为基于门开始信号来控制第一和第二节点的电压的节点控制器和连接到与输出节点相邻的至少两个栅极线的开关单元，以及 被配置为使用时钟信号向至少两个相邻的栅极线顺序地提供具有不同脉冲宽度的栅极导通电压脉冲。
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