-
公开(公告)号:US07463067B2
公开(公告)日:2008-12-09
申请号:US11537781
申请日:2006-10-02
申请人: Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
发明人: Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
IPC分类号: H03K19/094
CPC分类号: H03K19/177
摘要: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.
摘要翻译: 用于结合硬件和软件技术的FPGA架构的开关块,以减少主动和待机泄漏功率。
-
公开(公告)号:US20070085563A1
公开(公告)日:2007-04-19
申请号:US11537781
申请日:2006-10-02
申请人: Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
发明人: Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
IPC分类号: H03K19/177
CPC分类号: H03K19/177
摘要: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.
摘要翻译: 用于结合硬件和软件技术的FPGA架构的开关块,以减少主动和待机泄漏功率。
-