-
1.发明授权Method for implementing functional changes into a design layout of an integrated device, in particular a system-on-chip, by means of mask programmable filling cells 有权通过掩模可编程填充单元将功能变化实现为集成器件（特别是片上系统）的设计布局的方法公开(公告)号：US08214774B2
公开(公告)日：2012-07-03
申请号：US12648953
申请日：2009-12-29
Applicant: Valentina Nardone , Stefania Stucchi , Luca Ciccarelli , Lorenzo Calí
Inventor： Valentina Nardone , Stefania Stucchi , Luca Ciccarelli , Lorenzo Calí
IPC: G06F17/50 , G06F19/00 , G01R31/28 , H03K19/173 , H01L25/00
CPC classification number: G06F17/5068
Abstract: A System-on-Chip (SoC) may include logic blocks connected to each other and to external connections, and a hardware debug infrastructure logic connected to the logic blocks and for performing functional changes to a design layout of the SoC. The hardware debug infrastructure logic may include software re-configurable modules based upon the logic blocks obtained from substituting a mask programmable ECO base cell configured as a functional logic cell for a logic cell in the design layout.
Abstract translation: 片上系统（SoC）可以包括彼此连接和连接到外部连接的逻辑块，以及连接到逻辑块的硬件调试基础设施逻辑，并且用于对SoC的设计布局进行功能改变。 硬件调试基础架构逻辑可以包括基于从设计布局中的逻辑单元的配置为功能逻辑单元的掩模可编程ECO基本单元获得的逻辑块的软件可重新配置的模块。
-
公开(公告)号：US07683674B2
公开(公告)日：2010-03-23
申请号：US11810792
申请日：2007-06-06
Applicant: Luca Ciccarelli , Andrea Lodi
Inventor： Luca Ciccarelli , Andrea Lodi
IPC: H03K19/094
CPC classification number: H03K17/693 , H03K19/17736 , H03K19/17784
Abstract: An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.
Abstract translation: 本发明的实施例涉及一种用于连接第一，第二和第三线路的T开关，并且包括输入部分，其依次包括第一，第二和第三输入传输晶体管，每个输入传输晶体管将相应的线路与T形开关的第一内部节点连接， 开关，输出部分依次包括第一，第二和第三输出传输晶体管，每个输出传输晶体管将相应的线路与T开关的第二内部节点连接，以及单个缓冲级，其连接到第一和第二参考电压并插入在 第一和第二内部节点。
-
3.发明授权Switch block and corresponding switch matrix, in particular for FPGA architectures 有权开关块和相应的开关矩阵，特别适用于FPGA架构公开(公告)号：US07463055B2
公开(公告)日：2008-12-09
申请号：US11215301
申请日：2005-08-30
Applicant: Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
Inventor： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
IPC: H03K19/173
CPC classification number: H03K19/17736
Abstract: A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.
Abstract translation: 适于实现连接到其上的互连线之间的连接的开关块，所述互连线至少包括连接到互连线的开关块，并且至少包括缓冲级，并且依次连接到多个晶体管。 切换块包括插入在多个SRAM单元与切换块的多个晶体管的各控制端之间的解码级。
-
公开(公告)号：US20080225987A1
公开(公告)日：2008-09-18
申请号：US12006102
申请日：2007-12-28
Applicant: Alberto Fazzi , Luca Ciccarelli , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
Inventor： Alberto Fazzi , Luca Ciccarelli , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
IPC: H04L23/00
CPC classification number: H03K19/018521 , H03K3/356165
Abstract: An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage. The recovery stage comprises a first feedback loop connected to the first feedback node and acting in such a way to recover a received voltage signal and a feedback loop connected to the second feedback node of the state control stage and acting in such a way to deactivate the recovery feedback on the receiver node and guarantee that the receiver node is let in a high impedance state.
Abstract translation: 本发明的实施例涉及一种异步互连系统，其包括插入在相应的第一和第二电压基准之间的发射机电路和接收机电路，并且具有以电容方式耦合的相应的发射机和接收机节点。 接收器电路包括：恢复级，其插入在接收器电路的第一和第二参考电压之间并连接到接收器节点; 并且状态控制级又连接在连接到恢复级的接收器电路的第一和第二参考电压之间，与提供第一控制信号的第一反馈节点相对应，并且具有以反馈方式连接到恢复的第二反馈节点 阶段。 恢复阶段包括连接到第一反馈节点的第一反馈环路，并以这样一种方式起作用以恢复接收到的电压信号和连接到状态控制级的第二反馈节点的反馈回路，并以这样的方式使其停用 对接收机节点进行恢复反馈，并保证接收机节点处于高阻抗状态。
-
公开(公告)号：US07808276B2
公开(公告)日：2010-10-05
申请号：US11519444
申请日：2006-09-11
Applicant: Luca Ciccarelli , Luca Magagni , Alberto Fazzi , Roberto Canegallo , Roberto Guerrieri
Inventor： Luca Ciccarelli , Luca Magagni , Alberto Fazzi , Roberto Canegallo , Roberto Guerrieri
IPC: H03K19/094
CPC classification number: H01L25/0657 , G06F13/4077 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
Abstract: Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The transmitter includes precharge and evaluation blocks connected to each other and to a transmitter clock terminal. The receiver includes a precharge block connected to a receiver clock terminal. The precharge blocks precharge an output terminal of the transmitter and an input terminal of the receiver, respectively, to a value corresponding to a first voltage reference during a low phase of the transmitter clock signal.
Abstract translation: 本发明的实施例涉及一种包括发射机和接收机的芯片到芯片通信系统，所述发射机和接收机被连接以接收相应的发射机和接收机时钟信号。 发射机包括彼此连接的预充电和评估块以及发射机时钟终端。 接收机包括连接到接收机时钟端口的预充电块。 预充电块在发送器时钟信号的低相位期间，将发送器的输出端子和接收器的输入端子分别预充电到对应于第一电压基准的值。
-
Patent Agency Ranking
6.发明申请METHOD FOR IMPLEMENTING FUNCTIONAL CHANGES INTO A DESIGN LAYOUT OF AN INTEGRATED DEVICE, IN PARTICULAR A SYSTEM-ON-CHIP, BY MEANS OF MASK PROGRAMMABLE FILLING CELLS 有权将功能变化实现为集成设备的特定布局的方法，特别是片上系统，通过可编程填充单元公开(公告)号：US20100201400A1
公开(公告)日：2010-08-12
申请号：US12648953
申请日：2009-12-29
Applicant: Valentina Nardone , Stefania Stucchi , Luca Ciccarelli , Lorenzo Cali
Inventor： Valentina Nardone , Stefania Stucchi , Luca Ciccarelli , Lorenzo Cali
CPC classification number: G06F17/5068
Abstract: A System-on-Chip (SoC) may include logic blocks connected to each other and to external connections, and a hardware debug infrastructure logic connected to the logic blocks and for performing functional changes to a design layout of the SoC. The hardware debug infrastructure logic may include software re-configurable modules based upon the logic blocks obtained from substituting a mask programmable ECO base cell configured as a functional logic cell for a logic cell in the design layout.
Abstract translation: 片上系统（SoC）可以包括彼此连接和连接到外部连接的逻辑块，以及连接到逻辑块的硬件调试基础设施逻辑，并且用于对SoC的设计布局进行功能改变。 硬件调试基础架构逻辑可以包括基于从设计布局中的逻辑单元的配置为功能逻辑单元的掩模可编程ECO基本单元获得的逻辑块的软件可重新配置的模块。
-
7.发明申请METHOD FOR DESIGNING A HIGH PERFORMANCE ASIC (APPLICATION-SPECIFIC INTEGRATED CIRCUIT) ACCELERATOR 有权设计高性能ASIC（应用特定集成电路）加速器的方法公开(公告)号：US20100169857A1
公开(公告)日：2010-07-01
申请号：US12648099
申请日：2009-12-28
Applicant: Fabio Campi , Claudio Mucci , Stefano Pucillo , Luca Ciccarelli , Valentina Nardone
Inventor： Fabio Campi , Claudio Mucci , Stefano Pucillo , Luca Ciccarelli , Valentina Nardone
CPC classification number: G06F17/5068 , G06F2217/64
Abstract: A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
Abstract translation: 一种用于设计用于数字信号处理的加速器的方法，包括通过用固定拓扑预先布置DSP加速器的控制逻辑来定义可完全预编程的软件，以获得完全预先布置的控制逻辑。 该方法还包括通过定制可配置布局区域来定义硬件可编程部分预布置的宏，从而基于与DSP加速器的应用相关的计算内核映射计算逻辑。 因此获得部分预先布置的计算逻辑。
-
公开(公告)号：US20100164547A1
公开(公告)日：2010-07-01
申请号：US12648075
申请日：2009-12-28
Applicant: Luca Ciccarelli , Lorenzo Cali , Massimiliano Innocenti , Claudio Mucci , Valentina Nardone , Matteo Pizzotti , Pankaj Rohilla
Inventor： Luca Ciccarelli , Lorenzo Cali , Massimiliano Innocenti , Claudio Mucci , Valentina Nardone , Matteo Pizzotti , Pankaj Rohilla
IPC: H01L25/00
CPC classification number: G06F17/5068 , H01L27/0207 , H01L27/11807
Abstract: A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates.
Abstract translation: 一种用于具有至少第一对CMOS晶体管和第二对CMOS晶体管的工程变更单（ECO）实现的基本单元，其特征在于，所述至少第一对CMOS晶体管具有公共栅极和所述至少第二对 的CMOS晶体管具有分离的栅极。
-
9.发明申请Switch block and corresponding switch matrix, in particular for FPGA architectures 有权开关块和相应的开关矩阵，特别适用于FPGA架构公开(公告)号：US20060103420A1
公开(公告)日：2006-05-18
申请号：US11215301
申请日：2005-08-30
Applicant: Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
Inventor： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
IPC: H03K19/177
CPC classification number: H03K19/17736
Abstract: A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.
Abstract translation: 适于实现连接到其上的互连线之间的连接的开关块，所述互连线至少包括连接到互连线的开关块，并且至少包括缓冲级，并且依次连接到多个晶体管。 切换块包括插入在多个SRAM单元与切换块的多个晶体管的各控制端之间的解码级。
-
10.发明授权公开(公告)号：US08910103B2
公开(公告)日：2014-12-09
申请号：US12648099
申请日：2009-12-28
Applicant: Fabio Campi , Claudio Mucci , Stefano Pucillo , Luca Ciccarelli , Valentina Nardone
Inventor： Fabio Campi , Claudio Mucci , Stefano Pucillo , Luca Ciccarelli , Valentina Nardone
CPC classification number: G06F17/5068 , G06F2217/64
Abstract: A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
Abstract translation: 一种用于设计用于数字信号处理的加速器的方法，包括通过用固定拓扑预先布置DSP加速器的控制逻辑来定义可完全预编程的软件，以获得完全预先布置的控制逻辑。 该方法还包括通过定制可配置布局区域来定义硬件可编程部分预布置的宏，从而基于与DSP加速器的应用相关的计算内核映射计算逻辑。 因此获得部分预先布置的计算逻辑。
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.01 seconds)
