公开(公告)号：US20180158800A1

公开(公告)日：2018-06-07

申请号：US15372246

申请日：2016-12-07

Applicant: Micron Technology, Inc.

Inventor： Adam S. El-Mansouri ,  Fuad Badrieh ,  Brent Keeth

IPC: H01L25/065 ,  G05F1/10

CPC classification number: H01L25/0657 ,  G05F1/10 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.

公开(公告)号：US20210227986A1

公开(公告)日：2021-07-29

申请号：US17165533

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri

IPC: A47C20/00 ,  G11C7/06 ,  A47C13/00 ,  A47C17/02 ,  G11C11/22 ,  H01L27/11502

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

公开(公告)号：US11074956B1

公开(公告)日：2021-07-27

申请号：US16806942

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Ferdinando Bedeschi ,  Suryanarayana B. Tatapudi ,  Hyunyoo Lee ,  Adam S. El-Mansouri

IPC: G11C11/22

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

公开(公告)号：US20200329881A1

公开(公告)日：2020-10-22

申请号：US16867420

申请日：2020-05-05

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri

IPC: A47C20/00 ,  G11C7/06 ,  A47C13/00 ,  A47C17/02 ,  G11C11/22 ,  H01L27/11502

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

公开(公告)号：US10802516B2

公开(公告)日：2020-10-13

申请号：US16190523

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Adam S. El-Mansouri ,  Fuad Badrieh ,  Brent Keeth

IPC: G05F1/10 ,  H01L25/065

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including, a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.

公开(公告)号：US10699755B2

公开(公告)日：2020-06-30

申请号：US16134732

申请日：2018-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Adam S. El-Mansouri ,  John D. Porter

IPC: G11C7/06 ,  G11C11/22 ,  G11C5/14 ,  G11C7/22

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.

公开(公告)号：US11514969B2

公开(公告)日：2022-11-29

申请号：US17381996

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Ferdinando Bedeschi ,  Suryanarayana B. Tatapudi ,  Hyunyoo Lee ,  Adam S. El-Mansouri

IPC: G11C11/22

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

公开(公告)号：US20220020415A1

公开(公告)日：2022-01-20

申请号：US17381996

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Ferdinando Bedeschi ,  Suryanarayana B. Tatapudi ,  Hyunyoo Lee ,  Adam S. El-Mansouri

IPC: G11C11/22

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

公开(公告)号：US20210383856A1

公开(公告)日：2021-12-09

申请号：US17409608

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri ,  Suryanarayana B. Tatapudi ,  John D. Porter

IPC: G11C11/22

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

公开(公告)号：US11134788B2

公开(公告)日：2021-10-05

申请号：US17165533

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri

IPC: G11C11/22 ,  A47C20/00 ,  G11C7/06 ,  A47C13/00 ,  A47C17/02 ,  H01L27/11502

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.