公开(公告)号：US20250078884A1

公开(公告)日：2025-03-06

申请号：US18948310

申请日：2024-11-14

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Brent Keeth ,  Matthew A. Prather

IPC: G11C7/10 ,  G11C5/04 ,  G11C7/22

Abstract: Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.

公开(公告)号：US11983059B2

公开(公告)日：2024-05-14

申请号：US17541524

申请日：2021-12-03

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: G06F1/3225 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F1/3225 ,  G06F13/1678 ,  G06F13/409

Abstract: The present disclosure includes apparatuses and methods related to a memory expansion card suitable for, relative to other memory solutions, a high-speed interface and low power consumption. The memory expansion card can have on-die error correction code (ECC) circuitry and, in some examples, additional on-board circuitry, components, or capability to manage, relative to other memory solutions, a large number of volatile or non-volatile memory devices. A memory expansion card may have a controller with a host interface capable of using or defined according to a quantity of bits (i.e., a bit width), which may be eight bits. The controller may coupled to memory devices via several channels, and each channel may have the bit width of the interface.

公开(公告)号：US11869622B2

公开(公告)日：2024-01-09

申请号：US17494606

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: G11C5/06 ,  G11C5/02 ,  G11C5/14

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C5/148

Abstract: Methods, systems, and devices for memory with fine grain architectures are described. An apparatus may include a memory device, a first organic substrate, and a second organic substrate. The first organic substrate may include a plurality of first conductive lines arranged with a first pitch that may power one or more components of the memory device. The second organic substrate may be coupled with the memory device and the first organic substrate. The second organic substrate may include a plurality of second conductive lines arranged with a second pitch smaller than the first pitch and may be configured to route signals between the memory device with a host device.

公开(公告)号：US11755515B2

公开(公告)日：2023-09-12

申请号：US17685212

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F13/28 ,  G06F12/10 ,  G06F13/16 ,  G06F3/06 ,  G06F12/1027 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F13/28 ,  G06F3/0659 ,  G06F3/0661 ,  G06F12/10 ,  G06F12/1027 ,  G06F13/1668 ,  H01L23/5385 ,  H01L23/5386 ,  G06F2212/65 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/0652 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

公开(公告)号：US11635910B2

公开(公告)日：2023-04-25

申请号：US17136728

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04

Abstract: Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

公开(公告)号：US11614875B2

公开(公告)日：2023-03-28

申请号：US17142837

申请日：2021-01-06

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  James Brian Johnson

IPC: G11C7/10 ,  G06F3/06 ,  H01L23/538 ,  H01L25/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/22 ,  G06F11/10 ,  H01L25/065 ,  H01L23/50 ,  G11C5/02 ,  G11C11/00 ,  H01L23/14 ,  G11C11/4097

Abstract: Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.

公开(公告)号：US20230063029A1

公开(公告)日：2023-03-02

申请号：US18048732

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: H01L25/065 ,  H01L27/02

Abstract: Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include a plurality of banks of memory cells. Each region may be associated with a data channel configured to communicate with a host device. In some examples, each channel of the array may include two or more data pins. The ratio of data pins per channel may be two or four in various examples. Other examples may include eight data pins per channel.

公开(公告)号：US11594462B2

公开(公告)日：2023-02-28

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20220415855A1

公开(公告)日：2022-12-29

申请号：US17682773

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/66

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

公开(公告)号：US11527510B2

公开(公告)日：2022-12-13

申请号：US15976580

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: H01L25/065 ,  H01L27/02 ,  H01L23/00 ,  H01L27/118

Abstract: Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include a plurality of banks of memory cells. Each region may be associated with a data channel configured to communicate with a host device. In some examples, each channel of the array may include two or more data pins. The ratio of data pins per channel may be two or four in various examples. Other examples may include eight data pins per channel.