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公开(公告)号：US20240160526A1
公开(公告)日：2024-05-16
申请号：US18416967
申请日：2024-01-19
Applicant: Micron Technology, Inc.
Inventor： Tal Sharifie , Chandrakanth Rapalli , Yoav Weinberg
CPC classification number: G06F11/1068 , G06F11/0793 , G06F11/1004
Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system may receive data units from a host device. A first controller of the memory system may generate a protocol unit using the data units. A second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. The memory system may perform error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.
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公开(公告)号：US20240231685A9
公开(公告)日：2024-07-11
申请号：US18048292
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0631 , G06F3/0673
Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
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公开(公告)号：US11914473B1
公开(公告)日：2024-02-27
申请号：US18048289
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Tal Sharifie , Chandrakanth Rapalli , Yoav Weinberg
CPC classification number: G06F11/1068 , G06F11/0793 , G06F11/1004
Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system may receive data units from a host device. A first controller of the memory system may generate a protocol unit using the data units. A second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. The memory system may perform error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.
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Patent Agency Ranking
公开(公告)号：US20250036526A1
公开(公告)日：2025-01-30
申请号：US18791729
申请日：2024-08-01
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F11/10
Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
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公开(公告)号：US20240396571A1
公开(公告)日：2024-11-28
申请号：US18672533
申请日：2024-05-23
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
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公开(公告)号：US12001279B2
公开(公告)日：2024-06-04
申请号：US18048284
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
CPC classification number: G06F11/1004 , H03M13/095 , H03M13/611 , G06F11/1008
Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
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公开(公告)号：US20240134740A1
公开(公告)日：2024-04-25
申请号：US18048284
申请日：2022-10-19
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
CPC classification number: H03M13/095 , H03M13/611
Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
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公开(公告)号：US11860714B1
公开(公告)日：2024-01-02
申请号：US18048286
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Yoav Weinberg , Chandrakanth Rapalli , Tal Sharifie
CPC classification number: G06F11/0766 , G06F11/1096
Abstract: Methods, systems, and devices for error notification using an external channel are described. In some cases, a memory system having a host-driven logical block interface may issue a notification of a detected error using an out of band channel. For example, after receiving a data unit from a host system but prior to storing the data in a memory array of the memory system, the memory system may transmit an acknowledgment to host system to indicate that the data was successfully received. As part of storing the data, the memory system may transfer the data along data paths between various components and perform parity checks at each component. If the memory system detects an error along a data path, the memory system may issue a notification of the error to the host system over the out of band channel.
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