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公开(公告)号：US12081236B2
公开(公告)日：2024-09-03
申请号：US18225841
申请日：2023-07-25
发明人： Se-Ho Myung , Kyung-Joong Kim , Hong-Sil Jeong
CPC分类号： H03M13/1148 , H03M13/611 , H04L1/0057 , H04L1/0068 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/6356 , H03M13/6362 , H04L1/0041
摘要： A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.
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公开(公告)号：US12063051B2
公开(公告)日：2024-08-13
申请号：US17917028
申请日：2020-04-14
申请人： NEC Corporation
发明人： Prakash Chaki
CPC分类号： H03M13/1108 , H03M13/096 , H03M13/13 , H03M13/611
摘要： A communication method and device which can improve error correction performance and power consumption without increasing hardware complexity is disclosed. A communication apparatus includes: a decoder for polar codes, that decodes a codeword in which a frame is partitioned according to a predetermined partitioning rule and each partition includes at least one check bit computed by a predefined checksum equation; a memory that stores a frozen set including frozen bit indices, a non-frozen set including non-frozen bit indices, and a susceptible to error (STE) set including STE indices susceptible to decoding error for each partition; and a controller configured to: compute a check sum of at least one decoded bit for each partition according to the predefined checksum equation; responsive to failure of checksum, initiate a recurrent decoding attempt on the partition; and perform a bit-inversion operation on at least one STE index in each recurrent decoding attempt.
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公开(公告)号：US20240250699A1
公开(公告)日：2024-07-25
申请号：US18594795
申请日：2024-03-04
发明人： Aaron P. Boehm , Scott E. Schaefer
CPC分类号： H03M13/159 , G06F11/073 , G06F11/0787 , H03M13/611
摘要： Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.
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公开(公告)号：US12040818B2
公开(公告)日：2024-07-16
申请号：US18046143
申请日：2022-10-12
发明人： Youngseok Jung
CPC分类号： H03M13/09 , H03M13/611 , H04L1/005
摘要： A method includes calculating a number of iterative detection and decoding (IDD) iterations and a number of decoding iterations for each of a plurality of channel coding units in a target codeword; calculating a demodulation time and a decoding time for the target codeword based on the number of IDD iterations and the number of decoding iterations for the target codeword; adding the target codeword to a codeword set, based on a demodulation time and a decoding time for codewords in the codeword set and the target codeword; and performing an IDD operation based on a number of IDD iterations and a number of decoding iterations.
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公开(公告)号：US11996862B2
公开(公告)日：2024-05-28
申请号：US17930310
申请日：2022-09-07
CPC分类号： H03M13/1111 , G06F9/546 , H03M13/611
摘要： Systems and methods are disclosed for implementing a high performance decoder. In certain embodiments, an apparatus may comprise a decoder circuit configured to decode a codeword of bits, including: a check node processor configured to provide a plurality of check to variable (c2v) messages to a variable node processor in parallel, the plurality of c2v messages including log likelihood ratio (LLR) data related a parity sum of multiple bits of the codeword; the variable node processor configured to generate a decision vector based on the plurality of c2v messages; and a convergence checker circuit configured to determine whether the codeword has been decoded based on the decision vector and output decoded data when the codeword has been decoded.
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公开(公告)号：US20240154624A1
公开(公告)日：2024-05-09
申请号：US18413007
申请日：2024-01-15
申请人： Silicon Motion, Inc.
发明人： Tsung-Chieh Yang , Hong-Jung Hsu
CPC分类号： H03M13/098 , G06F11/1072 , G06F11/108 , G11C11/5628 , G11C16/10 , H03M13/1515 , H03M13/611 , G11C16/26
摘要： A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
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公开(公告)号：US11960351B1
公开(公告)日：2024-04-16
申请号：US17897334
申请日：2022-08-29
CPC分类号： G06F11/0772 , G06F11/004 , G06F11/3068 , H03M13/1131 , H03M13/611
摘要： Systems and methods for propagating poison information are provided. Embodiments include receiving write data having a poison flag asserted indicating the data to be written to a memory device is erroneous. Embodiments further include converting the write data to a pre-fixed data pattern and generating a parity code, based upon, at least in part, the pre-fixed data pattern. Embodiments may also include injecting a correctable error into the write-data or parity code and writing the write data and parity code into the memory device. The correctable error injection may occur in the data or in the parity code and during the read the comparison may occur accordingly.
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公开(公告)号：US20240106460A1
公开(公告)日：2024-03-28
申请号：US17934910
申请日：2022-09-23
申请人： SK hynix Inc.
发明人： Fan Zhang , Hongwei Duan , Haobo Wang
CPC分类号： H03M13/1111 , H03M13/611
摘要： To improve error correction when errors occur in consecutive bits of user data, the user data can be stored in an interleaved manner. Data of a data unit can be interleaved to generate a permutated data unit. A checksum of the permutated data unit can then be calculated, and an error correction code can be generated over the data unit and the checksum. The error correction code can also be interleaved to generate a permutated error correction code. The permutated data unit, the checksum, and the permutated error correction code can then be concatenated to generate a storage data unit for storage in a memory.
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公开(公告)号：US11942966B2
公开(公告)日：2024-03-26
申请号：US17816320
申请日：2022-07-29
发明人： Aaron P. Boehm , Scott E. Schaefer
CPC分类号： H03M13/159 , G06F11/073 , G06F11/0787 , H03M13/611
摘要： Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.
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公开(公告)号：US20240097707A1
公开(公告)日：2024-03-21
申请号：US17949635
申请日：2022-09-21
发明人： Leon Zlotnik , Eyal En Gad
CPC分类号： H03M13/1111 , H03M13/1575 , H03M13/611
摘要： A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
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