公开(公告)号：US20190035439A1

公开(公告)日：2019-01-31

申请号：US16136068

申请日：2018-09-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TSUGIO TAKAHASHI ,  Zer Liang

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1003

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory; and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.