公开(公告)号：US11468923B2

公开(公告)日：2022-10-11

申请号：US16924023

申请日：2020-07-08

申请人： MICRON TECHNOLOGY, INC.

发明人： Tsugio Takahashi ,  Zer Liang

IPC分类号： G11C7/10

摘要： Apparatuses, mufti-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US11373725B2

公开(公告)日：2022-06-28

申请号：US16912214

申请日：2020-06-25

申请人： Micron Technology, Inc.

发明人： Zer Liang ,  Minari Arai ,  Takuya Nakanishi

IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C29/12 ,  G11C7/22 ,  G11C7/06

摘要： Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

公开(公告)号：US10109327B2

公开(公告)日：2018-10-23

申请号：US15626915

申请日：2017-06-19

申请人： MICRON TECHNOLOGY, INC.

发明人： Tsugio Takahashi ,  Zer Liang

IPC分类号： G11C7/00 ,  G11C7/10

摘要： Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US09466348B2

公开(公告)日：2016-10-11

申请号：US14565822

申请日：2014-12-10

申请人： MICRON TECHNOLOGY, INC.

发明人： Jacob Robert Anderson ,  Kang-Yong Kim ,  Tadashi Yamamoto ,  Zer Liang ,  Huy Vo

IPC分类号： G11C7/00 ,  G11C8/12 ,  G11C7/10 ,  G06F13/42

CPC分类号： G11C8/12 ,  G06F13/4234 ,  G11C7/00 ,  G11C7/10 ,  Y02D10/14 ,  Y02D10/151

摘要： Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

摘要翻译： 公开了包含命令解码器，芯片使能和信号截断电路的存储器。 一个这样的命令解码器电路可以包括命令解码器逻辑，其被配置为接收命令信号，并且响应于具有活动状态的片选信号而将解码的命令输出到互连总线。 解码器电路还可以基于接收到具有无效状态的片选信号来防止到互连总线的耦合命令。 具有控制逻辑的芯片使能电路被配置为接收芯片选择信号，并且响应于接收到有效命令而将芯片选择信号提供给互连总线。 芯片使能电路还可以基于无效命令信号的接收，防止从芯片使能信号将互连芯片选择信号耦合到互连总线。 信号截断电路可用于缩短和/或移位芯片选择信号以增加定时裕度并提高存储器执行命令的可靠性。

公开(公告)号：US20210407611A1

公开(公告)日：2021-12-30

申请号：US16912214

申请日：2020-06-25

申请人： Micron Technology, Inc.

发明人： Zer Liang ,  Minari Arai ,  Takuya Nakanishi

IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C29/12 ,  G11C7/22 ,  G11C7/06

摘要： Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

公开(公告)号：US20140269121A1

公开(公告)日：2014-09-18

申请号：US13804461

申请日：2013-03-14

申请人： MICRON TECHNOLOGY, INC.

发明人： Tsugio Takahashi ,  Zer Liang

IPC分类号： G11C7/22

CPC分类号： G11C7/1039 ,  G11C7/1003

摘要： Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

摘要翻译： 公开了一种用于控制多存储器系统中的数据定时的装置，多存储器系统和方法。 示例性装置包括多个存储单元。 在示例性装置中，多个存储单元的存储单元包括被配置为基于行控制信号和列控制信号向数据流水线提供相关联的读取数据的存储器。 存储器单元还包括被配置为将行控制信号和列控制信号提供给存储器的本地控制逻辑，以及耦合在本地控制逻辑和存储器之间的可配置延迟电路，其被配置为将列控制信号的接收延迟到 记忆。

公开(公告)号：US20170287531A1

公开(公告)日：2017-10-05

申请号：US15626915

申请日：2017-06-19

申请人： MICRON TECHNOLOGY, INC.

发明人： Tsugio Takahashi ,  Zer Liang

IPC分类号： G11C7/10

CPC分类号： G11C7/1039 ,  G11C7/1003

摘要： Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US09715909B2

公开(公告)日：2017-07-25

申请号：US13804461

申请日：2013-03-14

申请人： Micron Technology, Inc.

发明人： Tsugio Takahashi ,  Zer Liang

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/1039 ,  G11C7/1003

摘要： Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configure d to delay receipt of the column control signals to the memory.

公开(公告)号：US20200342920A1

公开(公告)日：2020-10-29

申请号：US16924023

申请日：2020-07-08

申请人： MICRON TECHNOLOGY, INC.

发明人： Tsugio Takahashi ,  Zer Liang

IPC分类号： G11C7/10

摘要： Apparatuses, mufti-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US10748584B2

公开(公告)日：2020-08-18

申请号：US16136068

申请日：2018-09-19

申请人： MICRON TECHNOLOGY, INC.

发明人： Tsugio Takahashi ,  Zer Liang

IPC分类号： G11C7/10

摘要： Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.