公开(公告)号：US09905288B2

公开(公告)日：2018-02-27

申请号：US15435383

申请日：2017-02-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seung-Woo Ryu ,  Sang-Kyu Kang

IPC分类号： G11C8/00 ,  G11C11/4096 ,  G11C11/4076 ,  G11C8/18 ,  G06F1/12 ,  G06F1/08

CPC分类号： G11C11/4096 ,  G06F1/08 ,  G06F1/12 ,  G11C7/1003 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4076 ,  G11C17/16 ,  G11C29/023 ,  G11C2029/0411

摘要： A semiconductor memory device includes a memory cell array and a control logic circuit. The control logic circuit controls access to the memory cell array based on a command and an address. The semiconductor memory device performs a write operation to write data in the memory cell array and performs a read operation to read data from the memory cell array in synchronization with a clock signal from an external memory controller. The semiconductor memory device performs the write operation and the read operation in different data strobe modes in which the semiconductor memory device uses different numbers of data strobe signals according to a frequency of the clock signal.

公开(公告)号：US09792965B2

公开(公告)日：2017-10-17

申请号：US14737147

申请日：2015-06-11

申请人： Rambus Inc.

发明人： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC分类号： G11C7/10 ,  G11C5/04

CPC分类号： G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

摘要： A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US09691444B2

公开(公告)日：2017-06-27

申请号：US14076985

申请日：2013-11-11

申请人： Micron Technology, Inc.

发明人： Timothy M. Hollis

IPC分类号： G11C5/04 ,  G11C7/10 ,  G11C5/02

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C7/1003

摘要： Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.

公开(公告)号：US09672910B2

公开(公告)日：2017-06-06

申请号：US14248377

申请日：2014-04-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Theodore Antonakopoulos ,  Nikolaos Papandreou ,  Charalampos Pozidis

IPC分类号： G06F12/00 ,  G11C14/00 ,  G11C7/10 ,  G11C11/56 ,  G11C13/00 ,  G11C5/06

CPC分类号： G11C14/009 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1003 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004

摘要： A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.

公开(公告)号：US20160148653A1

公开(公告)日：2016-05-26

申请号：US15011383

申请日：2016-01-29

申请人： INTEL CORPORATION

发明人： Bill NALE

IPC分类号： G11C5/14

CPC分类号： G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

摘要： Provided are a method and apparatus for using a pre-clock enable (pre-CKE) command for power management modes. A host memory controller sends a pre-CKE command to a memory module over a bus indicating at least one power management operation to perform. The host memory controller further asserts a clock enable (CKE) signal to the memory module over the bus after sending the pre-CKE command to cause a memory module controller to execute the indicated at least one power management operation in response to the CKE signal.

摘要翻译： 提供了一种用于对电源管理模式使用前置时钟使能（pre-CKE）命令的方法和装置。 主机存储器控制器通过总线向存储器模块发送预CKE命令，指示执行至少一个电源管理操作。 主机存储器控制器在发送预先CKE命令之后进一步通过总线断言对存储器模块的时钟使能（CKE）信号，以使存储器模块控制器响应于CKE信号执行所指示的至少一个电源管理操作。

公开(公告)号：US09159374B2

公开(公告)日：2015-10-13

申请号：US13665181

申请日：2012-10-31

申请人： NovaChips Canada Inc.

发明人： Jin-Ki Kim ,  DaeHee Yi ,  HyoShin Kim

IPC分类号： G11C5/04 ,  G11C7/10 ,  H05K5/00

CPC分类号： G11C5/04 ,  G11C7/1003

摘要： A mass storage memory module system including a memory module having memory holding members which can be connected to each other, and removably connected to a memory controller. One or more modular memory holding members can be connected to each other to expand the overall storage capacity of the memory module. The presently described expandable memory module does not have a storage capacity limit. A memory holding member includes a plate, a plane, a board and another material having at least one memory device, or, on which at least one memory device is held or to which at least one memory device is mounted.

摘要翻译： 一种大容量存储器模块系统，包括具有能够彼此连接的存储器保持部件的存储器模块，并且可移除地连接到存储器控制器。 一个或多个模块化存储器保持构件可以彼此连接以扩展存储器模块的总体存储容量。 目前描述的可扩展存储器模块不具有存储容量限制。 存储器保持构件包括板，平面，板和具有至少一个存储器件的另一种材料，或者在其上保持至少一个存储器件或至少一个存储器件被安装在该存储器件上。

公开(公告)号：US20150279475A1

公开(公告)日：2015-10-01

申请号：US14738819

申请日：2015-06-12

申请人： WONSEOK LEE ,  YOUNGKUG MOON

发明人： WONSEOK LEE ,  YOUNGKUG MOON

IPC分类号： G11C16/28 ,  G06F12/02 ,  G11C14/00

CPC分类号： G11C16/28 ,  G06F5/10 ,  G06F12/0246 ,  G06F13/1668 ,  G06F2212/7208 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1673 ,  G11C13/003 ,  G11C14/0045

摘要： A memory system is provided, which includes a nonvolatile memory module including a plurality of nonvolatile memory devices, and a memory module controller configured to control the nonvolatile memory module. At least two nonvolatile memory devices of the plurality of nonvolatile memory devices are configured to store serial presence detect (SPD) information. The memory module controller is configured to read the SPD information from the nonvolatile memory module and to set a communication mode with the nonvolatile memory module based on the read SPD information.

摘要翻译： 提供一种存储器系统，其包括包括多个非易失性存储器件的非易失性存储器模块以及被配置为控制非易失性存储器模块的存储器模块控制器。 多个非易失性存储器件中的至少两个非易失性存储器件被配置为存储串行存在检测（SPD）信息。 存储器模块控制器被配置为从非易失性存储器模块读取SPD信息，并且基于读取的SPD信息设置与非易失性存储器模块的通信模式。

公开(公告)号：US20140325124A1

公开(公告)日：2014-10-30

申请号：US14248377

申请日：2014-04-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Theodore Antonakopoulos ,  Nikolaos Papandreou ,  Charalampos Pozidis

IPC分类号： G06F3/06 ,  G11C14/00

CPC分类号： G11C14/009 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1003 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004

摘要： A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.

摘要翻译： 一种用于将数据存储在多个存储器芯片中的存储器系统。 存储器系统包括K组的存储器芯片，其中K组的每组包括存储器芯片的数量M，其中N = K·M; 以及一个信号处理单元，具有数目为L的用于N个存储器芯片的信号处理数据的信号处理引擎，并且具有数据链接接口用于与每个K组进行对接。

公开(公告)号：US08825967B2

公开(公告)日：2014-09-02

申请号：US13401087

申请日：2012-02-21

申请人： Pyeon Hong Beom

发明人： Pyeon Hong Beom

IPC分类号： G06F12/00

CPC分类号： G11C7/1003 ,  G06F13/1668 ,  G11C7/1075

摘要： A memory device, comprising a first control input port, a second control input port, a third control input port, a data input port, a data output port, an internal memory and control circuitry. The control circuitry is responsive to a control signal on the first control input port to capture command and address information via the data input port. When the command is a read command, the control circuitry is further responsive to a read control signal on the second control input port to transfer data associated with the address information from the internal memory onto the data output port. When the command is a write command, the control circuitry is responsive to a write control signal on the third control input port to write data captured via the data input port into the internal memory at a location associated with the address information.

摘要翻译： 一种存储器件，包括第一控制输入端口，第二控制输入端口，第三控制输入端口，数据输入端口，数据输出端口，内部存储器和控制电路。 控制电路响应于第一控制输入端口上的控制信号，以经由数据输入端口捕获命令和地址信息。 当命令是读取命令时，控制电路还响应于第二控制输入端口上的读取控制信号将与地址信息相关联的数据从内部存储器传送到数据输出端口。 当命令是写命令时，控制电路响应于第三控制输入端口上的写入控制信号，将与数据输入端口捕获的数据写入与地址信息相关联的位置的内部存储器。

公开(公告)号：US20130151757A1

公开(公告)日：2013-06-13

申请号：US13401087

申请日：2012-02-21

申请人： Pyeon Hong Beom

发明人： Pyeon Hong Beom

IPC分类号： G06F12/00

CPC分类号： G11C7/1003 ,  G06F13/1668 ,  G11C7/1075

摘要： A memory device, comprising a first control input port, a second control input port, a third control input port, a data input port, a data output port, an internal memory and control circuitry. The control circuitry is responsive to a control signal on the first control input port to capture command and address information via the data input port. When the command is a read command, the control circuitry is further responsive to a read control signal on the second control input port to transfer data associated with the address information from the internal memory onto the data output port. When the command is a write command, the control circuitry is responsive to a write control signal on the third control input port to write data captured via the data input port into the internal memory at a location associated with the address information.

摘要翻译： 一种存储器件，包括第一控制输入端口，第二控制输入端口，第三控制输入端口，数据输入端口，数据输出端口，内部存储器和控制电路。 控制电路响应于第一控制输入端口上的控制信号，以经由数据输入端口捕获命令和地址信息。 当命令是读取命令时，控制电路还响应于第二控制输入端口上的读取控制信号将与地址信息相关联的数据从内部存储器传送到数据输出端口。 当命令是写命令时，控制电路响应于第三控制输入端口上的写入控制信号，将与数据输入端口捕获的数据写入与地址信息相关联的位置的内部存储器。