公开(公告)号：US11508449B2

公开(公告)日：2022-11-22

申请号：US17249433

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US20220310166A1

公开(公告)日：2022-09-29

申请号：US17670037

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Zhengyi Zhang ,  Tomoko Ogura Iwasaki

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26

Abstract: Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.

公开(公告)号：US11087851B2

公开(公告)日：2021-08-10

申请号：US16895025

申请日：2020-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhengyi Zhang ,  Dan Xu ,  Tomoko Ogura Iwasaki

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30

Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.