公开(公告)号：US20230197164A1

公开(公告)日：2023-06-22

申请号：US18076537

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

IPC: G11C16/12 ,  G11C16/28 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/12 ,  G11C16/28 ,  G11C16/08 ,  G11C16/30

Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

公开(公告)号：US20220199175A1

公开(公告)日：2022-06-23

申请号：US17249433

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/08

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US11901010B2

公开(公告)日：2024-02-13

申请号：US17247576

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/30 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

公开(公告)号：US11508449B2

公开(公告)日：2022-11-22

申请号：US17249433

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US20250149094A1

公开(公告)日：2025-05-08

申请号：US19008495

申请日：2025-01-02

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30

Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

公开(公告)号：US12217801B2

公开(公告)日：2025-02-04

申请号：US18076537

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30

Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

公开(公告)号：US20230044240A1

公开(公告)日：2023-02-09

申请号：US17970459

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US11967387B2

公开(公告)日：2024-04-23

申请号：US17970459

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US20240120010A1

公开(公告)日：2024-04-11

申请号：US18545888

申请日：2023-12-19

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

公开(公告)号：US20220189555A1

公开(公告)日：2022-06-16

申请号：US17247576

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.