公开(公告)号：US5857002A

公开(公告)日：1999-01-05

申请号：US698637

申请日：1996-08-16

申请人： Constantin Michael Melas

发明人： Constantin Michael Melas

IPC分类号： H04L25/493 ,  H04L25/34 ,  H04L25/49

CPC分类号： H04L25/493

摘要： A method and apparatus for decoding a partial response encoded signal to generate a decoded signal. The first stage of the apparatus, a first delay filter, receives the partial response encoded signal and filters it with a delay characteristic of (1-D.sup.2)(1+D). The second stage, a timing system, generates a digital signal representative of the first filtered signal. The timing system includes an equalizer with an EPR4 equalization characteristic. The third stage, a second delay filter, filters the signal with a delay characteristic of 1-D. The final stage, a partial Viterbi decoder, generates the decoded signal.

摘要翻译： 一种解码部分响应编码信号以产生解码信号的方法和装置。 装置的第一阶段是第一延迟滤波器，接收部分响应编码信号，并以（1-D2）（1 + D）的延迟特性对其进行滤波。 第二级定时系统产生代表第一滤波信号的数字信号。 定时系统包括具有EPR4均衡特性的均衡器。 第三级，第二延迟滤波器以1-D的延迟特性对信号进行滤波。 最后一个部分维特比解码器产生解码信号。

公开(公告)号：US06404831B1

公开(公告)日：2002-06-11

申请号：US09167728

申请日：1998-10-07

申请人： Constantin Michael Melas

发明人： Constantin Michael Melas

IPC分类号： H04B110

CPC分类号： G11B20/10212 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/1803 ,  H04L7/042 ,  H04L7/046

摘要： The present invention is a data detection channel with improved detection reliability and better immunity to signal dropout and noise, that has reduced data redundancy. The data detection channel includes a preamp/filter, a sample/quantizer, an equalizer, a timing recovery circuit and a digital detection filter. The digital detection filter includes a finite impulse response filter, a synchronization and windowing device and a data detection circuit. The a finite impulse response filter has a plurality of coefficients and stores a plurality of channel data samples. On each cycle of the sampling clock, the finite impulse response filter is operable to input and store a channel data sample and output a sum signal representing a sum of each product of each coefficient multiplied by a corresponding stored channel data sample. The synchronization and windowing device is operable to receive the sum signal each sampling clock cycle and output the sum signal, if it corresponds to a symbol. The data detection circuit is operable to receive a sum signal that corresponds to a symbol and outputting digital data represented by the symbol.

摘要翻译： 本发明是具有改善的检测可靠性和对信号丢失和噪声的更好抗扰性的数据检测通道，其具有减少的数据冗余性。 数据检测通道包括前置放大器/滤波器，采样/量化器，均衡器，定时恢复电路和数字检测滤波器。 数字检测滤波器包括有限脉冲响应滤波器，同步和加窗装置以及数据检测电路。 有限脉冲响应滤波器具有多个系数并存储多个信道数据采样。 在采样时钟的每个周期上，有限脉冲响应滤波器可操作以输入和存储信道数据采样，并输出表示每个系数的乘积与相应存储的信道数据样本相乘的和的和信号。 同步和加窗装置可操作以接收每个采样时钟周期的和信号，并输出和信号，如果它对应于符号。 数据检测电路可操作以接收与符号对应的和信号并输出​​由符号表示的数字数据。