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    TRANSITION ENFORCING CODING RECEIVER FOR SAMPLING VECTOR SIGNALS WITHOUT USING CLOCK AND DATA RECOVERY
    3.
    发明申请
    TRANSITION ENFORCING CODING RECEIVER FOR SAMPLING VECTOR SIGNALS WITHOUT USING CLOCK AND DATA RECOVERY 有权

    公开(公告)号：US20170126444A1

    公开(公告)日：2017-05-04

    申请号：US15407265

    申请日：2017-01-17

    申请人： MEDIATEK INC.

    发明人： Ching-Hsiang Chang

    IPC分类号： H04L25/493

    CPC分类号： H04L25/493 ,  G06F13/4278 ,  H03L7/0807 ,  H04L25/4917

    摘要： A transition enforcing coding (TEC) receiver includes a delay line circuit, a transition detection circuit, a data sampling circuit, and a skew calibration circuit. The delay line circuit employs a calibrated delay setting to delay a plurality of vector signals to generate a plurality of delayed vector signals under a normal mode, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing, wherein the sampling timing is determined based on an output of the transition detection circuit. The skew calibration circuit sets the calibrated delay setting under a calibration mode, wherein transition skew between different delayed vector signals is reduced by the calibrated delay setting under the normal mode.

    Communication method based on bi-level binary digital baseband symbols
    4.
    发明授权
    Communication method based on bi-level binary digital baseband symbols 有权
    基于双电平二进制数字基带符号的通信方法

    公开(公告)号：US09509344B1

    公开(公告)日：2016-11-29

    申请号：US14840937

    申请日：2015-08-31

    申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    发明人： Peng Guo

    IPC分类号： H04L25/34 ,  H04B1/04

    CPC分类号： H04L25/493

    摘要： The invention discloses a communication method using dual-level and binary digital baseband symbols which represents information by durations of a high level and a low level instead of by a high level and a low level in conventional digital baseband symbol design. In the invention, waveforms of a symbol 0 and a symbol 1 are determined according to durations of a high level and a low level, a transmitter generates a corresponding digital baseband signal in terms of a binary data to be transmitted according to the defined waveforms, and a receiver determines a symbol 0 or a symbol 1 according to waveform of a received digital baseband signal. The invention realizes bit synchronization of a receiver and a transmitter without extracting a bit synchronization clock from a received signal by the receiver, and a bit rate thereof is higher than that of Manchester under a same signal bandwidth.

    摘要翻译： 本发明公开了一种使用双电平和二进制数字基带符号的通信方法，其代表了传统数字基带符号设计中高电平和低电平的持续时间而不是高电平和低电平的信息。 在本发明中，根据高电平和低电平的持续时间来确定符号0和符号1的波形，发送器根据定义的波形根据要发送的二进制数据产生对应的数字基带信号， 并且接收机根据接收的数字基带信号的波形确定符号0或符号1。 本发明实现接收机和发射机的比特同步，而不用接收机从接收到的信号中提取比特同步时钟，并且其比特率高于曼彻斯特在相同信号带宽下的比特率。

    LOW-SKEW COMMUNICATION SYSTEM
    5.
    发明申请
    LOW-SKEW COMMUNICATION SYSTEM 审中-公开
    低通道通信系统

    公开(公告)号：US20160197560A1

    公开(公告)日：2016-07-07

    申请号：US14894538

    申请日：2014-06-17

    申请人： MASCHINENFABRIK REINHAUSEN GMBH

    发明人： Robert John LEEDHAM ,  Matteo VIT ,  Stephen PARKER ,  Ivan CRONIN

    IPC分类号： H02M7/00 ,  G05B15/02

    CPC分类号： H02M7/00 ,  G05B15/02 ,  G06F13/4295 ,  H02M2001/0012 ,  H04L12/40013 ,  H04L25/493 ,  Y02D10/14 ,  Y02D10/151

    摘要： The invention generally relates to power converters, and more particularly to a communications method for controlling at least one power switching device of a power converter, a communications system for a power converter, and a power converter comprising the communications system. For example there is provided a communications method for controlling at least one power switching device of a power converter, the method comprising: inputting a signal to a transmit end of a communications link; inputting data to the transmit end of the communications link; determining whether the signal comprises a transition; when said determination indicates that the signal comprises a transition, transmitting the signal comprising the transition into a communications channel of the communications link, wherein the transmitted signal is delayed by a predetermined time delay relative to the inputted signal, said predetermined time delay to allow said determining; transmitting the data on the communications channel, wherein when said determination indicates that the signal comprises a transition the transmitting the data is delayed until after said transmitting the signal; and if the signal has been transmitted, receiving the transmitted signal at the receive end of the communications link and controlling at least one said power switching device dependent on said received signal.

    摘要翻译： 本发明一般涉及功率转换器，更具体地说，涉及用于控制功率转换器的至少一个功率开关器件，用于功率转换器的通信系统以及包括该通信系统的功率转换器的通信方法。 例如，提供了一种用于控制功率转换器的至少一个功率开关装置的通信方法，所述方法包括：将信号输入到通信链路的发送端; 将数据输入到通信链路的发送端; 确定信号是否包括转换; 当所述确定指示信号包括转换时，将包括转换的信号发送到通信链路的通信信道中，其中发送信号相对于输入信号延迟预定的时间延迟，所述预定时间延迟允许所述 决定; 在所述通信信道上发送数据，其中当所述确定指示所述信号包括转换时，发送所述数据被延迟直到所述发送所述信号为止; 并且如果已经发送了信号，则在通信链路的接收端处接收发送的信号，并根据所接收的信号控制至少一个所述功率开关装置。

    Compact and fast N-factorial single data rate clock and data recovery circuits
    7.
    发明授权
    Compact and fast N-factorial single data rate clock and data recovery circuits 有权
    紧凑，快速的N因子单数据速率时钟和数据恢复电路

    公开(公告)号：US09313058B2

    公开(公告)日：2016-04-12

    申请号：US14459132

    申请日：2014-08-13

    申请人： QUALCOMM Incorporated

    发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee

    IPC分类号： H04B1/00 ,  H04L25/40 ,  H04L7/04 ,  H03L7/00 ,  H04L7/027 ,  H04L7/033 ,  H04L25/493

    CPC分类号： H04L25/40 ,  H03L7/00 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14 ,  H04L25/493

    摘要： A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.

    摘要翻译： 多个线路接口被配置为在多个线路接口上接收扩展信号。 扩展信号携带符号，其中连续符号之间保证符号到符号状态转换。 扩展信号由包括第一线路接口上的第一信号的多个转换信号定义。 基于第一信号的第一实例和第一信号的延迟的第二实例之间的比较来提取时钟信号。 基于时钟信号对第一信号的延迟第二实例进行采样以提供符号输出。 时钟提取电路还适于基于多个转换信号之间的第二信号的第一实例与第二信号的延迟的第二实例之间的附加比较来生成时钟信号，其中第一和第二信号是并发的 通过不同线路接口接收的信号。

    Cross-channel data communication with data phase-locked loop
    9.
    发明授权
    Cross-channel data communication with data phase-locked loop 有权
    与数据锁相环路进行跨频道数据通讯

    公开(公告)号：US09166775B2

    公开(公告)日：2015-10-20

    申请号：US14153294

    申请日：2014-01-13

    申请人： Hamilton Sundstrand Corporation

    发明人： Paul J. Leblanc

    IPC分类号： H03D3/24 ,  H04L7/033 ,  H03L7/089

    CPC分类号： H04L7/0331 ,  H03L7/0891 ,  H04L7/033 ,  H04L25/493

    摘要： A data communication system includes a unit that receives edge-encoded data from a data link. The unit includes a counter, a data bit reader, and a phase-locked loop. The counter counts at a sampling frequency between a minimum value and an end-count value. The data bit reader is connected to receive the edge-encoded data. The data bit reader samples the edge-encoded data at the sampling frequency to detect data bits of the edge-encoded data. The phase-locked loop updates the end-count value if consecutive bits of the data bits are detected prior to an expected iteration of the counter. The phase-locked loop also updates the end-count value if consecutive bits of the data bits are detected later than the expected iteration of the first counter.

    摘要翻译： 数据通信系统包括从数据链路接收边缘编码数据的单元。 该单元包括计数器，数据位读取器和锁相环。 计数器以最小值和最终计数值之间的采样频率进行计数。 数据位读取器被连接以接收边缘编码数据。 数据位读取器以采样频率对边缘编码数据进行采样，以检测边缘编码数据的数据位。 如果在计数器的预期重复之前检测到数据位的连续位，则锁相环更新结束计数值。 如果比第一个计数器的预期迭代更晚地检测数据位的连续位，则锁相环还会更新结束计数值。

    SIMULTANEOUS TRANSMISSION OF CLOCK AND BIDIRECTIONAL DATA OVER A COMMUNICATION CHANNEL
    10.
    发明申请
    SIMULTANEOUS TRANSMISSION OF CLOCK AND BIDIRECTIONAL DATA OVER A COMMUNICATION CHANNEL 有权
    通讯通道同时传输时钟和双向数据

    公开(公告)号：US20150270946A1

    公开(公告)日：2015-09-24

    申请号：US14731342

    申请日：2015-06-04

    申请人： Silicon Image, Inc.

    发明人： Inyeol Lee ,  Baegin Sung ,  Hanwoong Sohn ,  Shinje Tahk ,  Sun Woo Baek ,  Chandlee B. Harrell

    IPC分类号： H04L7/00 ,  H04L25/493 ,  H04B3/23 ,  H04L7/04 ,  H04L25/49

    CPC分类号： H04L7/0087 ,  H04B3/23 ,  H04B7/015 ,  H04L7/0278 ,  H04L7/033 ,  H04L7/042 ,  H04L25/4904 ,  H04L25/493

    摘要： Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

    摘要翻译： 本发明的实施例一般涉及通过通信信道同时传输时钟和双向数据。 发射装置的实施例包括调制器，用于产生包括时钟信号和数据信号的调制信号，时钟信号由调制信号的第一信号边沿调制，数据信号由第二信号的位置调制 调制信号的边缘; 在通信信道上驱动调制信号的驱动器; 回波消除器，用于减去通信信道上的反射信号; 以及数据恢复模块，用于恢复在通信信道上接收到的信号，所述接收信号通过归零（RZ）编码进行编码，该信号与在通信信道上驱动调制信号同时接收。