公开(公告)号：US11309904B1

公开(公告)日：2022-04-19

申请号：US17183919

申请日：2021-02-24

Applicant: Marvell Asia Pte Ltd.

Inventor： Ray Luan Nguyen ,  Geoffrey Hatcher

IPC: H03M1/12 ,  H03M1/28 ,  H03M1/36 ,  H03M1/06

Abstract: A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.

公开(公告)号：US11157037B1

公开(公告)日：2021-10-26

申请号：US17097791

申请日：2020-11-13

Applicant: MARVELL ASIA PTE, LTD.

Inventor： Ray Luan Nguyen ,  Geoffrey O. Hatcher

IPC: G06F1/08 ,  G06F1/06

Abstract: A multi-layer time-interleaving (TI) device and method of operation therefor. This device includes a plurality of TI layers configured to receive a plurality of input clock signals and to output a plurality of output clock signals, each of which can be configured to drive subsequent devices. The layers include at least a first and second layer including a fine-grain propagation device and a barrel-shifting propagation device configured to retime the plurality of input clock signals to produce divided output clock signals. The device can include additional barrel-shifting propagation devices to time interleave an initial two layers to produce one or more additional layers. Using negative phase stepping, the plurality of output clock signals is produced with optimal timing margin and synchronized on a single clock edge.