公开(公告)号：US20240146548A1

公开(公告)日：2024-05-02

申请号：US17933892

申请日：2022-09-21

Applicant: Meta Platforms Technologies, LLC

Inventor： Sudhir Satpathy ,  Renji George Thomas ,  Shrirang Madhav Yardi

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/30

CPC classification number: H04L9/3278 ,  H04L9/0866 ,  H04L9/30

Abstract: A testing system includes one or more processors; and a memory storing instructions that, when executed, cause the one or more processors to: perform, on each array of an SRAM of a System-on-a-Chip (SoC), the SRAM having a plurality of arrays, one or more tests to determine one or more biased cells in the array, generate bias characteristics for each array of the SRAM based on the one or more biased cells of the array, compare bias characteristics of each of the plurality of arrays, select, based on the comparison, an array of the plurality of arrays as a Physically Unclonable Function (PUF) array, and store an identifier of the PUF array into a memory of the SoC.

公开(公告)号：US20240095376A1

公开(公告)日：2024-03-21

申请号：US17933897

申请日：2022-09-21

Applicant: Meta Platforms Technologies, LLC

Inventor： Sudhir Satpathy ,  Renji George Thomas ,  Shrirang Madhav Yardi

IPC: G06F21/60 ,  G06F21/55 ,  G06F21/64

CPC classification number: G06F21/602 ,  G06F21/554 ,  G06F21/64 ,  G06F2221/0755

Abstract: An example method includes identifying, by processing circuitry, a Physically Unclonable Function (PUF) array selected from a static random-access memory (SRAM) device of a System-on-a-Chip (SoC); reading, by the processing circuitry, from a memory, helper data associated with the PUF array and usable for generating a cryptographic key based on the PUF array; determining, by the processing circuitry, whether the helper data associated with the PUF array has been altered after its initial generation by a test system; and in response to determining that the helper data associated with the PUF array has been altered, disabling access to data, software, or functions protected by the cryptographic key generated based on the PUF array.

公开(公告)号：US11601532B2

公开(公告)日：2023-03-07

申请号：US16860991

申请日：2020-04-28

Applicant: Meta Platforms Technologies, LLC

Inventor： Dinesh Patil ,  Wojciech Stefan Powiertowski ,  Neeraj Upasani ,  Sudhir Satpathy

IPC: H04L69/22 ,  H04L9/40 ,  H04B7/26 ,  H04L45/745 ,  G06F13/28 ,  G06F13/40 ,  G06F21/60 ,  G06F21/79 ,  H04W28/14

Abstract: In an example of the described techniques, a wireless communication system includes first memory, second memory, a first microcontroller, and a second microcontroller. The first microcontroller manages drivers for a wireless transceiver and direct data movement between the wireless transceiver and the first memory. The second microcontroller communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory. Additionally, the second microcontroller direct data movement between the second memory and the first memory.

公开(公告)号：US20240289466A1

公开(公告)日：2024-08-29

申请号：US18175358

申请日：2023-02-27

Applicant: Meta Platforms Technologies, LLC

Inventor： Wojciech Stefan Powiertowski ,  Avdhesh Chhodavdia ,  Gregory Edward Ehmann ,  Nagendra Gupta Modadugu ,  Sudhir Satpathy

IPC: G06F21/60 ,  G06F21/55 ,  G06F21/79

CPC classification number: G06F21/602 ,  G06F21/556 ,  G06F21/79

Abstract: In one embodiment, a method by an Energy processing Unit (EPU) of a computing system includes detecting an event that triggers an integrity verification on a block of the local memory, determining that a hash for the block of the local memory is available, causing data corresponding to the block of the local memory to be read from a source location in response to the determination, performing an in-line hash operation on the data corresponding to the block of the local memory, and comparing an output of the in-line hash operation and a known hash for the block of the local memory.

公开(公告)号：US20240013443A1

公开(公告)日：2024-01-11

申请号：US17860829

申请日：2022-07-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Sudhir Satpathy ,  Zhi Zhou ,  Richard Lawrence Greene

IPC: G06T9/00 ,  G06T3/40

CPC classification number: G06T9/001 ,  G06T3/40 ,  G06T19/006

Abstract: In an embodiment, a system includes a buffer configured to store a plurality of pixel blocks of an image, a first processor unit configured to receive a pixel block of the of the plurality of pixel blocks and select whether to separately encode or jointly encode pixel components of the pixel block by computing eigenvalues for the pixel components, a second processor unit configured to compute, responsive to the first processing unit selecting to jointly encode the pixel block, (i) an eigenvector for the pixel components of the pixel block based on the eigenvalues and (ii) endpoints on the eigenvector for encoding the pixel components, an encoder unit configured to encode, responsive to the first processing unit selecting to jointly encode the pixel block, the pixel components of the pixel block jointly based on the eigenvector and the endpoints.

公开(公告)号：US20230053821A1

公开(公告)日：2023-02-23

申请号：US18048302

申请日：2022-10-20

Applicant: Meta Platforms Technologies, LLC

Inventor： Sudhir Satpathy ,  Wojciech Stefan Powiertowski ,  Neeraj Upasani ,  Dinesh Patil

IPC: G06F12/14 ,  G06F12/1081 ,  G06T19/00 ,  G06F15/78 ,  G02B27/01 ,  H04L9/40

Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.

公开(公告)号：US11470061B2

公开(公告)日：2022-10-11

申请号：US16749250

申请日：2020-01-22

Applicant: Meta Platforms Technologies, LLC

Inventor： Sudhir Satpathy ,  Wojciech Stefan Powiertowski ,  Neeraj Upasani

IPC: H04L9/40 ,  G06F3/01 ,  G06F12/1081 ,  G02B27/01 ,  G06F9/54 ,  G06F15/78 ,  G06F9/48

Abstract: This disclosure describes systems on a chip (SOCs) that prevent side channel attacks on encryption and decryption engines of an electronic device. The SoCs of this disclosure concurrently operate key-diverse encryption and decryption datapaths to obfuscate the power trace signature exhibited by the device that includes the SoC. An example SoC includes an encryption engine configured to encrypt transmission (Tx) channel data using an encryption key and a decryption engine configured to decrypt encrypted received (Rx) channel data using a decryption key that is different from the encryption key. The SoC also includes a scheduler configured to establish concurrent data availability between the encryption and decryption engines and activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data using the decryption key that is different from the encryption key.