公开(公告)号：US12032839B2

公开(公告)日：2024-07-09

申请号：US16947432

申请日：2020-07-31

Applicant: Meta Platforms Technologies, LLC

Inventor： Shrirang Madhav Yardi ,  Gregory Edward Ehmann ,  Ennio Salemi ,  George Spatz ,  Jeffrey Ryden

IPC: G06F3/06 ,  G06F1/28 ,  G06T19/00 ,  G06F3/01

CPC classification number: G06F3/0634 ,  G06F1/28 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0673 ,  G06T19/006 ,  G06F3/011

Abstract: The disclosure describes techniques for hierarchical power management of memory of an artificial reality system to reduce power consumption by the memory. An example device may be a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content for display. The device includes memory divided into multiple memory blocks configurable to operate in a plurality of power modes. The device also includes memory block controllers controlling memory blocks. Each memory block controller controls which power mode in which the corresponding memory block is to operate, independent of any of the other memory blocks. The device includes a memory power controller configured to configure control registers of the memory block controllers to direct the memory block controllers to select one of the plurality of power modes for the memory blocks when the memory blocks are not being accessed.

公开(公告)号：US11474970B2

公开(公告)日：2022-10-18

申请号：US16726492

申请日：2019-12-24

Applicant: Meta Platforms Technologies, LLC

Inventor： Jun Wang ,  Neeraj Upasani ,  Wojciech Stefan Powiertowski ,  Drew Eric Wingard ,  Gregory Edward Ehmann ,  Marco Brambilla ,  Minli Lin ,  Miguel Angel Guerrero

IPC: G06F15/163 ,  H04N13/344 ,  G06F15/173 ,  G06F15/167

Abstract: The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

公开(公告)号：US20240289466A1

公开(公告)日：2024-08-29

申请号：US18175358

申请日：2023-02-27

Applicant: Meta Platforms Technologies, LLC

Inventor： Wojciech Stefan Powiertowski ,  Avdhesh Chhodavdia ,  Gregory Edward Ehmann ,  Nagendra Gupta Modadugu ,  Sudhir Satpathy

IPC: G06F21/60 ,  G06F21/55 ,  G06F21/79

CPC classification number: G06F21/602 ,  G06F21/556 ,  G06F21/79

Abstract: In one embodiment, a method by an Energy processing Unit (EPU) of a computing system includes detecting an event that triggers an integrity verification on a block of the local memory, determining that a hash for the block of the local memory is available, causing data corresponding to the block of the local memory to be read from a source location in response to the determination, performing an in-line hash operation on the data corresponding to the block of the local memory, and comparing an output of the in-line hash operation and a known hash for the block of the local memory.

公开(公告)号：US11487594B1

公开(公告)日：2022-11-01

申请号：US17303697

申请日：2021-06-04

Applicant: Meta Platforms Technologies, LLC

Inventor： Gregory Edward Ehmann

IPC: G06F3/00 ,  G06F9/54 ,  G06F5/06

Abstract: The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors and an inter-processor communication (IPC) unit. The IPC unit includes one or more doorbell registers, wherein each doorbell register is associated with a uniquely assigned source processor and a uniquely assigned target processor. Each doorbell register is further configured to store doorbell data indicative of whether an interrupt is a high priority interrupt or a low priority interrupt. The IPC unit may also include one or more FIFO (first-in first-out) memories configured to store data associated with each interrupt.