公开(公告)号：US07385433B2

公开(公告)日：2008-06-10

申请号：US11083531

申请日：2005-03-18

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: G05F1/10

CPC classification number: H03K17/162 ,  H03K17/063 ,  H03K2217/0018

Abstract: According to the invention a well-switching arrangement, with a semiconductor circuit including a switch having an input terminal, an output terminal and a body region and at least one comparator having a first input coupled to at least one of the terminals and a second input coupled to a positive voltage rail, and logic coupled to an output of the comparator and responsive to the output to selectively couple the body-well region to one of the terminals or to the positive voltage rail.

Abstract translation: 根据本发明，一种阱切换装置，其中半导体电路包括具有输入端子，输出端子和体区域的开关，以及至少一个比较器，其具有耦合到至少一个端子的第一输入端和第二输入端 耦合到正电压轨，以及耦合到比较器的输出的逻辑，并且响应于输出以选择性地将身体区域耦合到终端之一或正电压轨。

公开(公告)号：US06747515B2

公开(公告)日：2004-06-08

申请号：US09963023

申请日：2001-09-25

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: H03F345

CPC classification number: H03F3/45183 ,  H03F2203/45371 ,  H03F2203/45674 ,  H03G3/20

Abstract: A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if either of the outputs are greater than a reference voltage, a control signal is generated which is used to regulate the gain of the variable gain amplifier. In other embodiments, an analog OR function is used as an input to a conventional two input comparator in place of the three input comparator. In another embodiment, outputs of the variable gain amplifier are passed through switches to a scaling circuit which either voltage divides or amplifies and combines the outputs before application to a comparator. In each case, known asymmetries can be compensated for by independent gain control of each of the outputs of the variable gain differential amplifier.

Abstract translation: 用于调节可变差分增益放大器增益的电路。 在一个实施例中，全差分放大器放大可变增益放大器的输出。 全差分放大器的输出被施加到三个输入比较器，使得如果输出中的任一个大于参考电压，则产生用于调节可变增益放大器的增益的控制信号。 在其他实施例中，代替三个输入比较器，使用模拟OR功能作为常规两个输入比较器的输入。 在另一个实施例中，可变增益放大器的输出通过开关传递到缩放电路，电压分压或放大并将其应用于比较器之前的输出组合。 在每种情况下，可以通过可变增益差分放大器的每个输出的独立增益控制来补偿已知的不对称性。

公开(公告)号：US06605982B2

公开(公告)日：2003-08-12

申请号：US09895492

申请日：2001-06-29

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: G05F110

CPC classification number: G05F3/205

Abstract: An integrated circuit includes storage circuits comprising isolation transistors to which a certain bias voltage may be applied. The bias voltage is generated by a bias voltage generator. A boost circuit responds to initial bias voltage transition by generating a boost current that is applied to the isolation transistors with the transitioning bias voltage.

Abstract translation: 集成电路包括存储电路，该存储电路包括可施加一定偏置电压的隔离晶体管。 偏置电压由偏置电压发生器产生。 升压电路通过产生以过渡偏置电压施加到隔离晶体管的升压电流来响应初始偏置电压转换。

公开(公告)号：US06583651B1

公开(公告)日：2003-06-24

申请号：US10013215

申请日：2001-12-07

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: H03K522

CPC classification number: H03K5/08 ,  G01R19/16595

Abstract: A device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device has a differential amplifier configuration having an input to receive a comparison signal, a plurality of inputs to receive analog signals and a corresponding plurality of outputs to provide digital voltage signals. This device also has at least one logic circuit having a plurality of input terminals, each connected to a corresponding output of the differential amplifier configuration, and having at least one output terminal.

Abstract translation: 用于在一组模拟信号中选择具有最低或最高值的模拟信号的装置和方法。 在一个实施例中，该器件具有差分放大器配置，其具有用于接收比较信号的输入端，用于接收模拟信号的多个输入端和相应的多个输出端以提供数字电压信号。 该装置还具有至少一个具有多个输入端子的逻辑电路，每个输入端子连接到差分放大器配置的相应输出端，并具有至少一个输出端子。

公开(公告)号：US5726676A

公开(公告)日：1998-03-10

申请号：US459034

申请日：1995-05-31

Applicant: Michael J. Callahan, Jr. ,  Christopher A. Ludden

Inventor： Michael J. Callahan, Jr. ,  Christopher A. Ludden

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC classification number: G09G3/2011 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

公开(公告)号：US4315108A

公开(公告)日：1982-02-09

申请号：US2424

申请日：1979-01-10

Applicant: Gordon B. Hoffman ,  Michael J. Callahan, Jr.

Inventor： Gordon B. Hoffman ,  Michael J. Callahan, Jr.

IPC: H04M1/50

CPC classification number: H04M1/505

Abstract: A dual-tone multiple frequency signal generator is provided for use with telecommunications systems, data transfer systems and other applications. The tone encoding system utilizes MOS/LSI integrated circuitry on a single chip powered directly by telephone line voltages. An electronic keyboard circuit provides synchronized pulses to decode single-pole, single-throw keyboard switches by row and column. A crystal-controlled oscillator generates a reference frequency which is divided according to the row and column of an activated keyboard switch to obtain two pulse signals having frequencies representative of the activated switch. The outputs of the divider circuitry are fed to a programmed logic array which generates two digitally coded signals each representing a sinusoidal waveform. A digital-to-analog ladder network converts the digitally coded signals to continuous sine waves, and an operational amplifier combines the sinusoidal waveforms to provide a dual-tone output. The integrated circuitry also utilizes electronic switches for the common functions of tone transmission, including applying power to the oscillator, disconnecting the audio transmitter and attenuating the input to the receiver. Complementary-symmetry, metal-oxide semi-conductor elements implement the circuitry design with bi-polar transistors on the same chip performing some of the common function switching.

Abstract translation: 提供双音多频信号发生器用于电信系统，数据传输系统和其他应用。 音调编码系统在直接由电话线电压供电的单个芯片上使用MOS / LSI集成电路。 电子键盘电路提供同步脉冲，通过行和列解码单刀单掷键盘开关。 晶体振荡器产生根据激活的键盘开关的行和列分割的参考频率，以获得具有表示激活的开关的频率的两个脉冲信号。 分频器电路的输出被馈送到编程逻辑阵列，其产生每个表示正弦波形的两个数字编码信号。 数模转换梯形网将数字编码信号转换为连续正弦波，运算放大器组合正弦波形以提供双音输出。 集成电路还利用电子开关用于音调传输的共同功能，包括向振荡器施加电力，断开音频发射器并衰减到接收机的输入。 互补对称，金属氧化物半导体元件在同一芯片上实现具有双极晶体管的电路设计，执行一些通用功能切换。

公开(公告)号：US07057843B2

公开(公告)日：2006-06-06

申请号：US10447913

申请日：2003-05-28

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: G11B5/596

CPC classification number: G11B5/59605

Abstract: A servo control circuit provides seamless transition between seek and track modes while enabling both rapid seek mode operation and accurate tracking. The control circuit includes an analog-to-digital converter having a non-linear characteristic. The non-linear characteristic provides disproportionately large control voltages to derive speed and settling in the seek mode and essentially linear control voltages in the track mode to provide low noise and accurate tracking operation.

Abstract translation: 伺服控制电路提供搜索和跟踪模式之间的无缝转换，同时实现快速寻道模式操作和精确跟踪。 控制电路包括具有非线性特性的模数转换器。 非线性特性提供不成比例的大的控制电压，以在寻轨模式下导出速度和稳定，并且在轨道模式中提供基本上线性的控制电压，以提供低噪声和准确的跟踪操作。

公开(公告)号：US06927610B2

公开(公告)日：2005-08-09

申请号：US10912371

申请日：2004-08-05

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: H03B1/00 ,  H03K3/00 ,  H03K4/502 ,  H03K4/90 ,  H03K5/08 ,  H03K5/12 ,  H03K5/13 ,  H03K17/16

CPC classification number: H03K17/166 ,  H03K4/502 ,  H03K5/08 ,  H03K5/13

Abstract: Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.

Abstract translation: 用于确保用于从最大电压到最小电源电压（例如地）的功率驱动级的转换速率控制的电容器的高度线性放电的方法和结构。 电压斜坡发生器使用单个级联电流源来实现线性斜坡下降。

公开(公告)号：US06297698B1

公开(公告)日：2001-10-02

申请号：US09561093

申请日：2000-04-28

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: H03F345

CPC classification number: H03F3/45183 ,  H03F2203/45371 ,  H03F2203/45674 ,  H03G3/20

Abstract: A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if either of the outputs are greater than a reference voltage, a control signal is generated which is used to regulate the gain of the variable gain amplifier. In other embodiments, an analog OR function is used as an input to a conventional two input comparator in place of the three input comparator. In another embodiment, outputs of the variable gain amplifier are passed through switches to a scaling circuit which either voltage divides or amplifies and combines the outputs before application to a comparator. In each case, known asymmetries can be compensated for by independent gain control of each of the outputs of the variable gain differential amplifier.

Abstract translation: 用于调节可变差分增益放大器增益的电路。 在一个实施例中，全差分放大器放大可变增益放大器的输出。 全差分放大器的输出被施加到三个输入比较器，使得如果输出中的任一个大于参考电压，则产生用于调节可变增益放大器的增益的控制信号。 在其他实施例中，代替三个输入比较器，使用模拟OR功能作为常规两个输入比较器的输入。 在另一个实施例中，可变增益放大器的输出通过开关传递到缩放电路，电压分压或放大并将其应用于比较器之前的输出组合。 在每种情况下，可以通过可变增益差分放大器的每个输出的独立增益控制来补偿已知的不对称性。

公开(公告)号：US06208187B1

公开(公告)日：2001-03-27

申请号：US09326358

申请日：1999-06-04

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: H03K3286

CPC classification number: H03K3/02337 ,  H03K5/2481 ,  H03K5/249

Abstract: A high-gain comparator has a built-in hysteresis offset voltage generation feature. The comparator is characterized as having several elements, including a differential amplifier pair that is provided with first and second input voltages, an offset voltage element that creates an offset voltage between the first and second elements of the differential amplifier pair, an output generation element operably coupled to the differential amplifier pair that generates an output voltage of the comparator which is indicative of a voltage difference between the first and second input voltages, and a control element operably coupled to the output signal that controllably adjusts the offset voltage from a first state to a second state in accordance with the output signal to create a hysteresis condition of the comparator.

Abstract translation: 高增益比较器具有内置的滞后偏移电压产生功能。 比较器的特征在于具有若干元件，包括设置有第一和第二输入电压的差分放大器对，在差分放大器对的第一和第二元件之间产生偏移电压的偏移电压元件，可操作地输出的输出产生元件 耦合到所述差分放大器对，所述差分放大器对产生指示所述第一和第二输入电压之间的电压差的所述比较器的输出电压，以及可操作地耦合到所述输出信号的控制元件，所述控制元件可控地将所述偏移电压从第一状态调整到 根据输出信号的第二状态来产生比较器的滞后条件。