公开(公告)号：US20220342823A1

公开(公告)日：2022-10-27

申请号：US17302067

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Anna Scalesse ,  Umberto Siciliani ,  Carminantonio Manganelli

IPC: G06F12/0844

Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.