公开(公告)号：US20230367496A1

公开(公告)日：2023-11-16

申请号：US17663138

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Carla L. Christensen ,  Iolanda Del Villano ,  Lalla Fatima Drissi ,  Anna Scalesse ,  Maddalena Calzolari

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for block repurposing based on health metrics are described. The method may involve setting a storage state of a block of memory cells, the storage state corresponding to a storage density of the block of memory cells or an access mode of the block of memory cells. Further, the method may involve updating the storage state of the block of memory cells based on a health condition associated with the block of memory cells and accessing the block of memory cells based on the updated storage state of the block of memory cells.

公开(公告)号：US20240354027A1

公开(公告)日：2024-10-24

申请号：US18638476

申请日：2024-04-17

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Carla L. Christensen ,  Iolanda Del Villano ,  Lalla Fatima Drissi ,  Anna Scalesse ,  Maddalena Calzolari

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.

公开(公告)号：US20230367504A1

公开(公告)日：2023-11-16

申请号：US17663139

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Carla L. Christensen ,  Iolanda Del Villano ,  Lalla Fatima Drissi ,  Anna Scalesse ,  Maddalena Calzolari

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.

公开(公告)号：US20220406388A1

公开(公告)日：2022-12-22

申请号：US17736902

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Tao Liu ,  Ting Luo ,  Dionisio Minopoli ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari ,  Walter Di'Francesco ,  Antonino Pollio ,  Luigi Esposito ,  Anna Scalesse ,  Allison J. Olson ,  Anna Chiara Siviero

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

公开(公告)号：US12183407B2

公开(公告)日：2024-12-31

申请号：US17736902

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Tao Liu ,  Ting Luo ,  Dionisio Minopoli ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari ,  Walter Di Francesco ,  Antonino Pollio ,  Luigi Esposito ,  Anna Scalesse ,  Allison J. Olson ,  Anna Chiara Siviero

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

公开(公告)号：US11989443B2

公开(公告)日：2024-05-21

申请号：US17663139

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Carla L. Christensen ,  Iolanda Del Villano ,  Lalla Fatima Drissi ,  Anna Scalesse ,  Maddalena Calzolari

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.

公开(公告)号：US20230367495A1

公开(公告)日：2023-11-16

申请号：US17663137

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Lalla Fatima Drissi ,  Anna Scalesse ,  Iolanda Del Villano ,  Maddalena Calzolari ,  Chiara Cerafogli ,  Carla L. Christensen

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0679

Abstract: Methods, systems, and devices for host-enabled block swap techniques are described. In some examples, a host system may receive an indication of a health metric associated with a first physical block and a second physical block of a memory system, where a first logical block of the memory system is associated with a first type of data and is mapped to the first physical block, and where a second logical block of the memory system is associated with a second type of data. The host system may then determine that the health metric associated with the first physical block satisfies a threshold and may update a mapping associated with the first virtual block, the second virtual block, the first physical block, and the second physical block.

公开(公告)号：US20250044970A1

公开(公告)日：2025-02-06

申请号：US18797447

申请日：2024-08-07

Applicant: Micron Technology, Inc.

Inventor： Lalla Fatima Drissi ,  Anna Scalesse ,  Iolanda Del Villano ,  Maddalena Calzolari ,  Chiara Cerafogli ,  Carla L. Christensen

IPC: G06F3/06

Abstract: Methods, systems, and devices for host-enabled block swap techniques are described. In some examples, a host system may receive an indication of a health metric associated with a first physical block and a second physical block of a memory system, where a first logical block of the memory system is associated with a first type of data and is mapped to the first physical block, and where a second logical block of the memory system is associated with a second type of data. The host system may then determine that the health metric associated with the first physical block satisfies a threshold and may update a mapping associated with the first virtual block, the second virtual block, the first physical block, and the second physical block.

公开(公告)号：US12073100B2

公开(公告)日：2024-08-27

申请号：US17663137

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Lalla Fatima Drissi ,  Anna Scalesse ,  Iolanda Del Villano ,  Maddalena Calzolari ,  Chiara Cerafogli ,  Carla L. Christensen

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for host-enabled block swap techniques are described. In some examples, a host system may receive an indication of a health metric associated with a first physical block and a second physical block of a memory system, where a first logical block of the memory system is associated with a first type of data and is mapped to the first physical block, and where a second logical block of the memory system is associated with a second type of data. The host system may then determine that the health metric associated with the first physical block satisfies a threshold and may update a mapping associated with the first virtual block, the second virtual block, the first physical block, and the second physical block.

公开(公告)号：US11886346B2

公开(公告)日：2024-01-30

申请号：US17302067

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Anna Scalesse ,  Umberto Siciliani ,  Carminantonio Manganelli

IPC: G06F12/00 ,  G06F12/0844 ,  G06F3/06

CPC classification number: G06F12/0844 ,  G06F3/0659 ,  G06F2212/1021

Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.