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    DIRECT LOGICAL-TO-PHYSICAL ADDRESS MAPPING FOR SEQUENTIAL PHYSICAL ADDRESSES
    1.
    发明申请
    DIRECT LOGICAL-TO-PHYSICAL ADDRESS MAPPING FOR SEQUENTIAL PHYSICAL ADDRESSES 有权

    公开(公告)号：US20250028484A1

    公开(公告)日：2025-01-23

    申请号：US18781572

    申请日：2024-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Lalla Fatima Drissi ,  Doriana Tardio ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

    Adaptive block mapping
    3.
    发明授权
    Adaptive block mapping 有权

    公开(公告)号：US11922069B2

    公开(公告)日：2024-03-05

    申请号：US17750131

    申请日：2022-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Alberto Sassara ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Luigi Esposito ,  Paolo Papa ,  Salvatore Del Prete ,  Xiangang Luo ,  Xiaolai Zhu

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

    Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

    SYNCHRONIZING NAND LOGICAL-TO-PHYSICAL TABLE REGION TRACKING
    5.
    发明申请
    SYNCHRONIZING NAND LOGICAL-TO-PHYSICAL TABLE REGION TRACKING 审中-公开

    公开(公告)号：US20200142821A1

    公开(公告)日：2020-05-07

    申请号：US16075543

    申请日：2017-12-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guan Zhong Wang ,  Xinghui Duan ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

    IPC: G06F12/02 ,  G06F12/0873

    Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

    Controlling NAND operation latency
    6.
    发明授权
    Controlling NAND operation latency 有权

    公开(公告)号：US10552316B2

    公开(公告)日：2020-02-04

    申请号：US16024380

    申请日：2018-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Luigi Esposito ,  Xinghui Duan ,  Lucia Santojanni ,  Massimo Iaculo

    IPC: G06F12/02 ,  G11C16/10

    Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.

    Reading sequential data from memory using a pivot table
    10.
    发明授权
    Reading sequential data from memory using a pivot table 有权

    公开(公告)号：US11675709B2

    公开(公告)日：2023-06-13

    申请号：US17494740

    申请日：2021-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi

    IPC: G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F2212/657

    Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

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