公开(公告)号：US20240144985A1

公开(公告)日：2024-05-02

申请号：US18386518

申请日：2023-11-02

Applicant: Micron Technology, Inc.

Inventor： Erik V. Pohlmann

IPC: G11C7/10 ,  G11C8/18

CPC classification number: G11C7/1093 ,  G11C7/1063 ,  G11C7/1066 ,  G11C8/18

Abstract: Methods, systems, and devices for dynamic random access memory speed bin compatibility are described. For instance, a device (e.g., a memory device, a host device) may combine a first parameter with a second parameter to generate a third parameter, where the first parameter may be associated with a duration for a clock that is coupled with a memory array to perform a clock cycle and the second parameter may be associated with a timing constraint associated with initiating an access operation for the memory array. The device may determine a latency of a column address strobe based on the third parameter relative to (e.g., satisfying) a threshold value and may access one or more memory cells of the memory array based on the latency of the column address strobe.

公开(公告)号：US20230367709A1

公开(公告)日：2023-11-16

申请号：US18144655

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Scott E. Smith ,  Matthew A. Prather ,  Erik V. Pohlmann

IPC: G06F12/06 ,  G06F11/07

CPC classification number: G06F12/06 ,  G06F11/0727 ,  G06F2212/1032

Abstract: Methods, systems, and devices for write command timing enhancement are described. A host device may transmit (e.g., issue), to a memory device, an activation command and an associated write command according to a delay that is different (e.g., shorter) than a row access to column access delay associated with read commands. In some examples, the delay between the activation command and the associated write command may be a function of the row access to column access delay associated with read commands and one or more additional parameters, such as a timing constraint or a speed parameter of the memory device.

公开(公告)号：US20220246188A1

公开(公告)日：2022-08-04

申请号：US17649006

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Erik V. Pohlmann ,  Neal J. Koyle

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: Methods, systems, and devices for memory clock management and estimation procedures are described. A host device may determine a quantity of clock cycles associated with a duration for accessing a memory cell of a memory array based on truncating a value of a first parameter associated with another duration for a clock to perform a clock cycle. The host device may estimate a value of a second parameter related to (e.g., inversely proportional) to the truncated value of the first parameter and related to (e.g., directly proportional) to a correction factor, and may adjust (e.g., truncate) a third parameter to determine the quantity of clock cycles. Additionally or alternatively, the host device may adjust (e.g., perform a ceiling operation on) the second parameter to determine the quantity of clock cycles. The host device may access the memory cell based on the quantity of clock cycles.