公开(公告)号：US20170083260A1

公开(公告)日：2017-03-23

申请号：US14860326

申请日：2015-09-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni ,  Gianfranco Santopietro ,  Gianfranco Ferrante ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0643 ,  G06F3/061 ,  G06F3/0679

Abstract: A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component. Further, the one or more commands include metadata, attributes, or both related to the one or more blocks of data. The controller circuitry interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component. Further, the controller circuitry of the memory device has access to the metadata, attributes or both.

公开(公告)号：US20240061787A1

公开(公告)日：2024-02-22

申请号：US17890507

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0873

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F12/0873

Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.

公开(公告)号：US20230244414A1

公开(公告)日：2023-08-03

申请号：US18095771

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F12/0253 ,  G06F3/0604 ,  G06F3/0676 ,  G06F3/0679

Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.

公开(公告)号：US20220374163A1

公开(公告)日：2022-11-24

申请号：US17323974

申请日：2021-05-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.

公开(公告)号：US20210406169A1

公开(公告)日：2021-12-30

申请号：US16962726

申请日：2019-10-09

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Daniele Balluchi ,  Gianfranco Ferrante

IPC: G06F12/02 ,  G06F12/06

Abstract: A memory device is provided. The memory device comprises: a plurality of memory cells, each memory cell being programmable to at least two logic states, each logic state corresponding to a respective nominal electric resistance value of the memory cell, the plurality of memory cells comprising a first group of memory cells and a second group of memory cells, the memory cells of the second group being programmed to a predefined logic state of said at least two logic states; a memory controller coupled to the plurality of memory cells and configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation to assess the logic state thereof. The memory controller is further configured to: apply the reading voltage to the memory cells of the second group to assess the logic state thereof; if the logic state of at least one memory cell of the second group is assessed to be different from said predefined logic state, perform a refresh operation of the memory cells of the first group by applying thereto a recovery voltage higher than the reading voltage to assess the logic state thereof and then reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

公开(公告)号：US20180129442A1

公开(公告)日：2018-05-10

申请号：US15862472

申请日：2018-01-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni ,  Gianfranco Santopietro ,  Gianfranco Ferrante ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0643 ,  G06F3/061 ,  G06F3/0679

Abstract: A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. The contextual file system data includes file metadata, file attributes, or both that identify an association of the one or more blocks of data with a file. The file is made up of the one or more blocks of data. The controller identifies the association of the one or more blocks of data with the file and executes the one or more commands, such that the one or more blocks of data are stored in the memory device with a placement based upon the association

公开(公告)号：US11556275B2

公开(公告)日：2023-01-17

申请号：US17323974

申请日：2021-05-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.

公开(公告)号：US20210089443A1

公开(公告)日：2021-03-25

申请号：US17112268

申请日：2020-12-04

Applicant: Micron Technology, Inc.

Inventor： Gianfranco Ferrante ,  Dionisio Minopoli

IPC: G06F12/02

Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.

公开(公告)号：US09880772B2

公开(公告)日：2018-01-30

申请号：US14860326

申请日：2015-09-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni ,  Gianfranco Santopietro ,  Gianfranco Ferrante ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0643 ,  G06F3/061 ,  G06F3/0679

Abstract: A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component. Further, the one or more commands include metadata, attributes, or both related to the one or more blocks of data. The controller circuitry interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component. Further, the controller circuitry of the memory device has access to the metadata, attributes or both.