公开(公告)号：US11132311B2

公开(公告)日：2021-09-28

申请号：US16702980

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Gianfranco Ferrante ,  Antonino Caprí ,  Emanuele Confalonieri ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G06F13/42 ,  G06F13/32 ,  G06F13/22 ,  G06F9/38

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

公开(公告)号：US10534731B2

公开(公告)日：2020-01-14

申请号：US15924917

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Gianfranco Ferrante ,  Antonino Caprí ,  Emanuele Confalonieri ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G06F13/42 ,  G06F13/32 ,  G06F13/22 ,  G06F9/38

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

公开(公告)号：US20240168889A1

公开(公告)日：2024-05-23

申请号：US18428758

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0873

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F12/0873

Abstract: A method includes: creating a logical-to-physical address translation (L2P) bitmap for each respective virtual block programmed across a plane of multiple dice of a memory device, each L2P bitmap identifying logical addresses, within each respective L2P table of a plurality of L2P tables, that belong to a respective virtual block; creating a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table, of the plurality of L2P tables, based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular virtual block; and identifying and updating, by the processing device, an L2P bitmap associated with the particular virtual block for an L2P mapping corresponding to the entry.

公开(公告)号：US11928063B1

公开(公告)日：2024-03-12

申请号：US17890507

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F12/0873

Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.

公开(公告)号：US10860474B2

公开(公告)日：2020-12-08

申请号：US15841378

申请日：2017-12-14

Applicant: Micron Technology, Inc.

Inventor： Gianfranco Ferrante ,  Dionisio Minopoli

IPC: G06F12/02

Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.

公开(公告)号：US20190286586A1

公开(公告)日：2019-09-19

申请号：US15924917

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Gianfranco Ferrante ,  Antonino Caprí ,  Emanuele Confalonieri ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

公开(公告)号：US11768627B2

公开(公告)日：2023-09-26

申请号：US18095771

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0676 ,  G06F3/0679 ,  G06F12/0253

Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.

公开(公告)号：US11461228B2

公开(公告)日：2022-10-04

申请号：US17112268

申请日：2020-12-04

Applicant: Micron Technology, Inc.

Inventor： Gianfranco Ferrante ,  Dionisio Minopoli

IPC: G06F12/02

Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.

公开(公告)号：US20190188124A1

公开(公告)日：2019-06-20

申请号：US15841378

申请日：2017-12-14

Applicant: Micron Technology, Inc.

Inventor： Gianfranco Ferrante ,  Dionisio Minopoli

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.

公开(公告)号：US10175908B2

公开(公告)日：2019-01-08

申请号：US15862472

申请日：2018-01-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni ,  Gianfranco Santopietro ,  Gianfranco Ferrante ,  Emanuele Confalonieri

IPC: G06F3/06

Abstract: A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. The contextual file system data includes file metadata, file attributes, or both that identify an association of the one or more blocks of data with a file. The file is made up of the one or more blocks of data. The controller identifies the association of the one or more blocks of data with the file and executes the one or more commands, such that the one or more blocks of data are stored in the memory device with a placement based upon the association.