公开(公告)号：US11494319B1

公开(公告)日：2022-11-08

申请号：US17445271

申请日：2021-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaeil Kim ,  Suryanarayana B. Tatapudi

IPC: G06F13/16 ,  G11C11/4093 ,  G06F11/10

Abstract: A memory device may support multiple DQ maps. Two or more of the DQ maps may support memory operations using a same input-output width. In some examples, one or more components for supporting a DQ map for a different input-output width may be used to also support one or more of the DQ maps for the same-input output width.

公开(公告)号：US20220115054A1

公开(公告)日：2022-04-14

申请号：US17511489

申请日：2021-10-26

Applicant: Micron Technology, Inc.

Inventor： Jaeil Kim

IPC: G11C11/4076 ,  G11C29/50 ,  G11C11/408 ,  G11C29/02 ,  G11C7/22 ,  G11C11/4093

Abstract: Methods, systems, and devices for timing signal calibration for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous with an input signal. To support asynchronous timing, a timing signal generation component of a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. Delay components may have characteristics that are sensitive to fabrication or operational variability, such that timing signals may also be affected by such variability. In accordance with examples as disclosed herein, a memory device may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled based on a calibration operation of the memory device, which may improve an ability of the memory device to account for various sources of timing signal variability.